board/matrix_vision/mvblx/fpga.c

   1 /*
   2  * (C) Copyright 2002
   3  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4  * Keith Outwater, keith_outwater@mvis.com.
   5  *
   6  * (C) Copyright 2011
   7  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   8  * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  *
  28  */
  29
  30 #include <common.h>
  31 #include <ACEX1K.h>
  32 #include <command.h>
  33 #include <asm/gpio.h>
  34 #include <linux/byteorder/generic.h>
  35 #include "fpga.h"
  36
  37 #ifdef FPGA_DEBUG
  38 #define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
  39 #else
  40 #define fpga_debug(fmt, args...)
  41 #endif
  42
  43 Altera_CYC2_Passive_Serial_fns altera_fns = {
  44         fpga_null_fn,   /* Altera_pre_fn */
  45         fpga_config_fn,
  46         fpga_status_fn,
  47         fpga_done_fn,
  48         fpga_wr_fn,
  49         fpga_null_fn,
  50         fpga_null_fn,
  51 };
  52
  53 Altera_desc cyclone2 = {
  54         Altera_CYC2,
  55         fast_passive_parallel,
  56         Altera_EP3C5_SIZE,
  57         (void *) &altera_fns,
  58         NULL,
  59         0
  60 };
  61
  62 #define GPIO_RESET              43
  63 #define GPIO_DCLK               65
  64 #define GPIO_nSTATUS    157
  65 #define GPIO_CONF_DONE  158
  66 #define GPIO_nCONFIG    159
  67 #define GPIO_DATA0              54
  68 #define GPIO_DATA1              55
  69 #define GPIO_DATA2              56
  70 #define GPIO_DATA3              57
  71 #define GPIO_DATA4              58
  72 #define GPIO_DATA5              60
  73 #define GPIO_DATA6              61
  74 #define GPIO_DATA7              62
  75
  76 DECLARE_GLOBAL_DATA_PTR;
  77
  78 /* return FPGA_SUCCESS on success, else FPGA_FAIL
  79  */
  80 int mvblx_init_fpga(void)
  81 {
  82         fpga_debug("Initializing FPGA interface\n");
  83         fpga_init();
  84         fpga_add(fpga_altera, &cyclone2);
  85
  86         if (gpio_request(GPIO_DCLK, "dclk") ||
  87                         gpio_request(GPIO_nSTATUS, "nStatus") ||
  88 #ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
  89                         gpio_request(GPIO_CONF_DONE, "conf_done") ||
  90 #endif
  91                         gpio_request(GPIO_nCONFIG, "nConfig") ||
  92                         gpio_request(GPIO_DATA0, "data0") ||
  93                         gpio_request(GPIO_DATA1, "data1") ||
  94                         gpio_request(GPIO_DATA2, "data2") ||
  95                         gpio_request(GPIO_DATA3, "data3") ||
  96                         gpio_request(GPIO_DATA4, "data4") ||
  97                         gpio_request(GPIO_DATA5, "data5") ||
  98                         gpio_request(GPIO_DATA6, "data6") ||
  99                         gpio_request(GPIO_DATA7, "data7")) {
 100                 printf("%s: error requesting GPIOs.", __func__);
 101                 return FPGA_FAIL;
 102         }
 103
 104         /* set up outputs */
 105         gpio_direction_output(GPIO_DCLK,  0);
 106         gpio_direction_output(GPIO_nCONFIG, 0);
 107         gpio_direction_output(GPIO_DATA0, 0);
 108         gpio_direction_output(GPIO_DATA1, 0);
 109         gpio_direction_output(GPIO_DATA2, 0);
 110         gpio_direction_output(GPIO_DATA3, 0);
 111         gpio_direction_output(GPIO_DATA4, 0);
 112         gpio_direction_output(GPIO_DATA5, 0);
 113         gpio_direction_output(GPIO_DATA6, 0);
 114         gpio_direction_output(GPIO_DATA7, 0);
 115
 116         /* NB omap_free_gpio() resets to an input, so we can't
 117          * free ie. nCONFIG, or else the FPGA would reset
 118          * Q: presumably gpio_free() has the same effect?
 119          */
 120
 121         /* set up inputs */
 122         gpio_direction_input(GPIO_nSTATUS);
 123 #ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
 124         gpio_direction_input(GPIO_CONF_DONE);
 125 #endif
 126
 127         fpga_config_fn(0, 1, 0);
 128         udelay(60);
 129
 130         return FPGA_SUCCESS;
 131 }
 132
 133 int fpga_null_fn(int cookie)
 134 {
 135         return 0;
 136 }
 137
 138 int fpga_config_fn(int assert, int flush, int cookie)
 139 {
 140         fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
 141         if (flush) {
 142                 gpio_set_value(GPIO_nCONFIG, !assert);
 143                 udelay(1);
 144                 gpio_set_value(GPIO_nCONFIG, assert);
 145         }
 146
 147         return assert;
 148 }
 149
 150 int fpga_done_fn(int cookie)
 151 {
 152         int result = 0;
 153
 154         /* since revA of BLX, we will not get this signal. */
 155         udelay(10);
 156 #ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
 157         fpga_debug("not waiting for CONF_DONE.");
 158         result = 1;
 159 #else
 160         fpga_debug("CONF_DONE check ... ");
 161         if (gpio_get_value(GPIO_CONF_DONE))  {
 162                 fpga_debug("high\n");
 163                 result = 1;
 164         } else
 165                 fpga_debug("low\n");
 166         gpio_free(GPIO_CONF_DONE);
 167 #endif
 168
 169         return result;
 170 }
 171
 172 int fpga_status_fn(int cookie)
 173 {
 174         int result = 0;
 175         fpga_debug("STATUS check ... ");
 176
 177         result = gpio_get_value(GPIO_nSTATUS);
 178
 179         if (result < 0)
 180                 fpga_debug("error\n");
 181         else if (result > 0)
 182                 fpga_debug("high\n");
 183         else
 184                 fpga_debug("low\n");
 185
 186         return result;
 187 }
 188
 189 static inline int _write_fpga(u8 byte)
 190 {
 191         gpio_set_value(GPIO_DATA0, byte & 0x01);
 192         gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
 193         gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
 194         gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
 195         gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
 196         gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
 197         gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
 198         gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
 199
 200         /* clock */
 201         gpio_set_value(GPIO_DCLK, 1);
 202         udelay(1);
 203         gpio_set_value(GPIO_DCLK, 0);
 204         udelay(1);
 205
 206         return 0;
 207 }
 208
 209 int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
 210 {
 211         unsigned char *data = (unsigned char *) buf;
 212         int i;
 213         int headerlen = len - cyclone2.size;
 214
 215         if (headerlen < 0)
 216                 return FPGA_FAIL;
 217         else if (headerlen == sizeof(uint32_t)) {
 218                 const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
 219                 char fpgavers_str[fpgavers_len];
 220                 snprintf(fpgavers_str, fpgavers_len, "0x%08x",
 221                                 be32_to_cpup((uint32_t*)data));
 222                 setenv("fpgavers", fpgavers_str);
 223         }
 224
 225         fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
 226         for (i = headerlen; i < len; i++)
 227                 _write_fpga(data[i]);
 228         fpga_debug("-%s\n", __func__);
 229
 230         return FPGA_SUCCESS;
 231 }