board/mcc200/mcc200.c

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc5xxx.h>
  13 #include <pci.h>
  14 #include <asm/processor.h>
  15
  16 /* Two MT48LC8M32B2 for 32 MB */
  17 /* #include "mt48lc8m32b2-6-7.h" */
  18
  19 /* One MT48LC16M32S2 for 64 MB */
  20 /* #include "mt48lc16m32s2-75.h" */
  21 #if defined (CONFIG_MCC200_SDRAM)
  22 #include "mt48lc16m16a2-75.h"
  23 #else
  24 #include "mt46v16m16-75.h"
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 extern flash_info_t flash_info[];       /* FLASH chips info */
  30
  31 extern int do_auto_update(void);
  32 ulong flash_get_size (ulong base, int banknum);
  33
  34 #ifndef CONFIG_SYS_RAMBOOT
  35 static void sdram_start (int hi_addr)
  36 {
  37         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  38
  39         /* unlock mode register */
  40         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  41         __asm__ volatile ("sync");
  42
  43         /* precharge all banks */
  44         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  45         __asm__ volatile ("sync");
  46
  47 #if SDRAM_DDR
  48         /* set mode register: extended mode */
  49         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  50         __asm__ volatile ("sync");
  51
  52         /* set mode register: reset DLL */
  53         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  54         __asm__ volatile ("sync");
  55 #endif
  56
  57         /* precharge all banks */
  58         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  59         __asm__ volatile ("sync");
  60
  61         /* auto refresh */
  62         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  63         __asm__ volatile ("sync");
  64
  65         /* set mode register */
  66         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  67         __asm__ volatile ("sync");
  68
  69         /* normal operation */
  70         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  71         __asm__ volatile ("sync");
  72
  73         udelay(10);
  74 }
  75 #endif
  76
  77 /*
  78  * ATTENTION: Although partially referenced initdram does NOT make real use
  79  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  80  *            is something else than 0x00000000.
  81  */
  82
  83 phys_size_t initdram (int board_type)
  84 {
  85         ulong dramsize = 0;
  86         ulong dramsize2 = 0;
  87         uint svr, pvr;
  88 #ifndef CONFIG_SYS_RAMBOOT
  89         ulong test1, test2;
  90
  91         /* setup SDRAM chip selects */
  92         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  93         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  94         __asm__ volatile ("sync");
  95
  96         /* setup config registers */
  97         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  98         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  99         __asm__ volatile ("sync");
 100
 101 #if SDRAM_DDR
 102         /* set tap delay */
 103         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 104         __asm__ volatile ("sync");
 105 #endif
 106
 107         /* find RAM size using SDRAM CS0 only */
 108         sdram_start(0);
 109         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 110         sdram_start(1);
 111         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 112         if (test1 > test2) {
 113                 sdram_start(0);
 114                 dramsize = test1;
 115         } else {
 116                 dramsize = test2;
 117         }
 118
 119         /* memory smaller than 1MB is impossible */
 120         if (dramsize < (1 << 20)) {
 121                 dramsize = 0;
 122         }
 123
 124         /* set SDRAM CS0 size according to the amount of RAM found */
 125         if (dramsize > 0) {
 126                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 127         } else {
 128                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 129         }
 130
 131         /* let SDRAM CS1 start right after CS0 */
 132         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 133
 134         /* find RAM size using SDRAM CS1 only */
 135         if (!dramsize)
 136                 sdram_start(0);
 137         test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 138         if (!dramsize) {
 139                 sdram_start(1);
 140                 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 141         }
 142         if (test1 > test2) {
 143                 sdram_start(0);
 144                 dramsize2 = test1;
 145         } else {
 146                 dramsize2 = test2;
 147         }
 148
 149         /* memory smaller than 1MB is impossible */
 150         if (dramsize2 < (1 << 20)) {
 151                 dramsize2 = 0;
 152         }
 153
 154         /* set SDRAM CS1 size according to the amount of RAM found */
 155         if (dramsize2 > 0) {
 156                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 157                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 158         } else {
 159                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 160         }
 161
 162 #else /* CONFIG_SYS_RAMBOOT */
 163
 164         /* retrieve size of memory connected to SDRAM CS0 */
 165         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 166         if (dramsize >= 0x13) {
 167                 dramsize = (1 << (dramsize - 0x13)) << 20;
 168         } else {
 169                 dramsize = 0;
 170         }
 171
 172         /* retrieve size of memory connected to SDRAM CS1 */
 173         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 174         if (dramsize2 >= 0x13) {
 175                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 176         } else {
 177                 dramsize2 = 0;
 178         }
 179
 180 #endif /* CONFIG_SYS_RAMBOOT */
 181
 182         /*
 183          * On MPC5200B we need to set the special configuration delay in the
 184          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 185          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 186          *
 187          * "The SDelay should be written to a value of 0x00000004. It is
 188          * required to account for changes caused by normal wafer processing
 189          * parameters."
 190          */
 191         svr = get_svr();
 192         pvr = get_pvr();
 193         if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 194                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 195                 __asm__ volatile ("sync");
 196         }
 197
 198         return dramsize + dramsize2;
 199 }
 200
 201 int checkboard (void)
 202 {
 203 #if defined(CONFIG_PRS200)
 204         puts ("Board: PRS200\n");
 205 #else
 206         puts ("Board: MCC200\n");
 207 #endif
 208         return 0;
 209 }
 210
 211 int misc_init_r (void)
 212 {
 213         ulong flash_sup_end, snum;
 214
 215         /*
 216          * Adjust flash start and offset to detected values
 217          */
 218         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 219         gd->bd->bi_flashoffset = 0;
 220
 221         /*
 222          * Check if boot FLASH isn't max size
 223          */
 224         if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
 225                 /* adjust mapping */
 226                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 227                         START_REG(gd->bd->bi_flashstart);
 228                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 229                         STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
 230
 231                 /*
 232                  * Re-check to get correct base address
 233                  */
 234                 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
 235
 236                 /*
 237                  * Re-do flash protection upon new addresses
 238                  */
 239                 flash_protect (FLAG_PROTECT_CLEAR,
 240                                gd->bd->bi_flashstart, 0xffffffff,
 241                                &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 242
 243                 /* Monitor protection ON by default */
 244                 flash_protect (FLAG_PROTECT_SET,
 245                                CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 246                                &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 247
 248                 /* Environment protection ON by default */
 249                 flash_protect (FLAG_PROTECT_SET,
 250                                CONFIG_ENV_ADDR,
 251                                CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
 252                                &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 253
 254                 /* Redundant environment protection ON by default */
 255                 flash_protect (FLAG_PROTECT_SET,
 256                                CONFIG_ENV_ADDR_REDUND,
 257                                CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
 258                                &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 259         }
 260
 261         if (gd->bd->bi_flashsize > (32 << 20)) {
 262                 /* Unprotect the upper bank of the Flash */
 263                 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
 264                 flash_protect (FLAG_PROTECT_CLEAR,
 265                                flash_info[0].start[0] + flash_info[0].size / 2,
 266                                (flash_info[0].start[0] - 1) + flash_info[0].size,
 267                                &flash_info[0]);
 268                 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
 269                 printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
 270                 flash_info[0].size = 32 << 20;
 271                 for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
 272                         flash_info[0].start[snum] < flash_sup_end;
 273                         snum++);
 274                 flash_info[0].sector_count = snum;
 275         }
 276
 277 #ifdef CONFIG_AUTO_UPDATE
 278         do_auto_update();
 279 #endif
 280         return (0);
 281 }
 282
 283 #ifdef  CONFIG_PCI
 284 static struct pci_controller hose;
 285
 286 extern void pci_mpc5xxx_init(struct pci_controller *);
 287
 288 void pci_init_board(void)
 289 {
 290         pci_mpc5xxx_init(&hose);
 291 }
 292 #endif
 293
 294 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 295
 296 void init_ide_reset (void)
 297 {
 298         debug ("init_ide_reset\n");
 299
 300 }
 301
 302 void ide_set_reset (int idereset)
 303 {
 304         debug ("ide_reset(%d)\n", idereset);
 305
 306 }
 307 #endif
 308
 309 #if defined(CONFIG_CMD_DOC)
 310 void doc_init (void)
 311 {
 312         doc_probe (CONFIG_SYS_DOC_BASE);
 313 }
 314 #endif