board/micronas/vct/vcth/reg_fwsram.h

   1 /*
   2  * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3  *
   4  * Copyright (C) 2006 Micronas GmbH
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * Premium & Platinum register addresses/definitions seem to be
  11  * identical, so we only need to use one file for both platforms.
  12  */
  13
  14 #ifndef _REG_FWSRAM_H_
  15 #define _REG_FWSRAM_H_
  16
  17 #define FWSRAM_BASE                     0x00030000
  18
  19 /*  Relative offsets of the register adresses */
  20
  21 #define FWSRAM_SR_ADDR_OFFSET_OFFS      0x00002000
  22 #define FWSRAM_SR_ADDR_OFFSET(base)     ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
  23 #define FWSRAM_TOP_BOOT_LOG_OFFS        0x00002004
  24 #define FWSRAM_TOP_BOOT_LOG(base)       ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
  25 #define FWSRAM_TOP_ROM_KBIST_OFFS       0x00002008
  26 #define FWSRAM_TOP_ROM_KBIST(base)      ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
  27 #define FWSRAM_TOP_CID1_H_OFFS          0x0000200C
  28 #define FWSRAM_TOP_CID1_H(base)         ((base) + FWSRAM_TOP_CID1_H_OFFS)
  29 #define FWSRAM_TOP_CID1_L_OFFS          0x00002010
  30 #define FWSRAM_TOP_CID1_L(base)         ((base) + FWSRAM_TOP_CID1_L_OFFS)
  31 #define FWSRAM_TOP_CID2_H_OFFS          0x00002014
  32 #define FWSRAM_TOP_CID2_H(base)         ((base) + FWSRAM_TOP_CID2_H_OFFS)
  33 #define FWSRAM_TOP_CID2_L_OFFS          0x00002018
  34 #define FWSRAM_TOP_CID2_L(base)         ((base) + FWSRAM_TOP_CID2_L_OFFS)
  35 #define FWSRAM_TOP_TDO_CFG_OFFS         0x0000203C
  36 #define FWSRAM_TOP_TDO_CFG(base)        ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
  37 #define FWSRAM_TOP_GPIO2_0_CFG_OFFS     0x00002040
  38 #define FWSRAM_TOP_GPIO2_0_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
  39 #define FWSRAM_TOP_GPIO2_1_CFG_OFFS     0x00002044
  40 #define FWSRAM_TOP_GPIO2_1_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
  41 #define FWSRAM_TOP_GPIO2_2_CFG_OFFS     0x00002048
  42 #define FWSRAM_TOP_GPIO2_2_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
  43 #define FWSRAM_TOP_GPIO2_3_CFG_OFFS     0x0000204C
  44 #define FWSRAM_TOP_GPIO2_3_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
  45 #define FWSRAM_TOP_GPIO2_4_CFG_OFFS     0x00002050
  46 #define FWSRAM_TOP_GPIO2_4_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
  47 #define FWSRAM_TOP_GPIO2_5_CFG_OFFS     0x00002054
  48 #define FWSRAM_TOP_GPIO2_5_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
  49 #define FWSRAM_TOP_GPIO2_6_CFG_OFFS     0x00002058
  50 #define FWSRAM_TOP_GPIO2_6_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
  51 #define FWSRAM_TOP_GPIO2_7_CFG_OFFS     0x0000205C
  52 #define FWSRAM_TOP_GPIO2_7_CFG(base)    ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
  53 #define FWSRAM_TOP_SCL_CFG_OFFS         0x00002060
  54 #define FWSRAM_TOP_SCL_CFG(base)        ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
  55 #define FWSRAM_TOP_SDA_CFG_OFFS         0x00002064
  56 #define FWSRAM_TOP_SDA_CFG(base)        ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
  57 #define FWSRAM_NO_MCM_FLASH_OFFS        0x00002068
  58 #define FWSRAM_NO_MCM_FLASH(base)       ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
  59
  60 #endif