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* Code cleanup:
[u-boot.git] / board / mpc8260ads / mpc8260ads.c
1 /*
2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
8 *
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
11 *
12 * (C) Copyright 2003 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35 #include <common.h>
36 #include <ioports.h>
37 #include <mpc8260.h>
38 #include <i2c.h>
39 #include <spd.h>
40 #include <miiphy.h>
41
42 /*
43 * I/O Port configuration table
44 *
45 * if conf is 1, then that port pin will be configured at boot time
46 * according to the five values podr/pdir/ppar/psor/pdat for that entry
47 */
48
49 const iop_conf_t iop_conf_tab[4][32] = {
50
51 /* Port A configuration */
52 { /* conf ppar psor pdir podr pdat */
53 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
54 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
55 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
56 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
57 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
58 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
59 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
60 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
61 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
62 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
63 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
64 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
65 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
66 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
67 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
68 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
69 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
70 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
71 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
72 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
73 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
74 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
75 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
76 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
77 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
78 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
79 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
80 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
81 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
82 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
83 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
84 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
85 },
86
87 /* Port B configuration */
88 { /* conf ppar psor pdir podr pdat */
89 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
90 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
91 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
92 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
93 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
94 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
95 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
96 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
97 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
98 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
99 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
100 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
101 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
102 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
103 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
104 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
105 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
106 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
107 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
108 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
109 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
110 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
114 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
121 },
122
123 /* Port C */
124 { /* conf ppar psor pdir podr pdat */
125 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
126 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
127 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
128 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
129 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
130 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
131 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
132 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
133 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
134 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
135 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
136 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
137 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
138 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
139 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
140 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
141 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
142 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
143 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
144 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
145 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
146 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
147 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
148 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
149 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
150 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
151 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
152 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
153 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
154 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
155 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
156 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
157 },
158
159 /* Port D */
160 { /* conf ppar psor pdir podr pdat */
161 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
162 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
163 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
164 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
165 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
166 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
167 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
168 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
169 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
170 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
171 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
172 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
173 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
174 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
175 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
176 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
177 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
178 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
179 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
180 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
181 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
182 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
183 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
184 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
185 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
186 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
187 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
188 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
189 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
193 }
194 };
195
196 void reset_phy (void)
197 {
198 vu_long *bcsr = (vu_long *)CFG_BCSR;
199
200 /* reset the FEC port */
201 bcsr[1] &= ~FETH_RST;
202 udelay(2);
203 bcsr[1] |= FETH_RST;
204 udelay(1000);
205 #ifdef CONFIG_MII
206 /*
207 * Ethernet PHY is configured (by means of configuration pins)
208 * to work at 10Mb/s only. We reconfigure it using MII
209 * to advertise all capabilities, including 100Mb/s, and
210 * restart autonegotiation.
211 */
212 miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
213 miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
214 miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
215 #endif /* CONFIG_MII */
216 }
217
218 int board_pre_init (void)
219 {
220 vu_long *bcsr = (vu_long *)CFG_BCSR;
221
222 bcsr[1] = ~FETHIEN & ~RS232EN_1;
223
224 return 0;
225 }
226
227 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
228
229 long int initdram (int board_type)
230 {
231 volatile immap_t *immap = (immap_t *) CFG_IMMR;
232 volatile memctl8260_t *memctl = &immap->im_memctl;
233 volatile uchar *ramaddr, c = 0xff;
234
235 /* Initialisation is for 16MB DIMM the board is shipped with */
236 long int msize = 16;
237 uint or = 0xFF000CA0;
238 uint psdmr = CFG_PSDMR;
239 uint psrt = CFG_PSRT;
240
241 int i;
242
243 #ifndef CFG_RAMBOOT
244 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
245 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
246 immap->im_siu_conf.sc_tescr1 = 0x00004000;
247
248 memctl->memc_mptpr = CFG_MPTPR;
249 /* init local sdram, bank 4 */
250 memctl->memc_lsrt = 0x00000010;
251 memctl->memc_or4 = 0xFFC01480;
252 memctl->memc_br4 = 0x04001861;
253 memctl->memc_lsdmr = 0x2886A522;
254 ramaddr = (uchar *) CFG_LSDRAM_BASE;
255 *ramaddr = c;
256 memctl->memc_lsdmr = 0x0886A522;
257 for (i = 0; i < 8; i++) {
258 *ramaddr = c;
259 }
260 memctl->memc_lsdmr = 0x1886A522;
261 *ramaddr = c;
262 memctl->memc_lsdmr = 0x4086A522;
263
264 /* init sdram dimm */
265 #ifdef CONFIG_SPD_EEPROM
266 {
267 spd_eeprom_t spd;
268 uint pbi, bsel, rowst, lsb, tmp;
269
270 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
271
272 /* Bank-based interleaving is not supported for physical bank
273 sizes greater than 128MB which is encoded as 0x20 in SPD
274 */
275 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
276 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
277 or = ~(msize - 1) << 20; /* SDAM */
278 switch (spd.nbanks) { /* BPD */
279 case 2:
280 bsel = 1;
281 break;
282 case 4:
283 bsel = 2;
284 or |= 0x00002000;
285 break;
286 case 8:
287 bsel = 3;
288 or |= 0x00004000;
289 break;
290 }
291 lsb = 3; /* For 64-bit port, lsb is 3 bits */
292
293 if (pbi) { /* Bus partition depends on interleaving */
294 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
295 or |= (rowst << 9); /* ROWST */
296 } else {
297 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
298 or |= ((rowst * 2 - 12) << 9); /* ROWST */
299 }
300 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
301
302 psdmr = (pbi << 31); /* PBI */
303 /* Bus multiplexing parameters */
304 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
305 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
306 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
307
308 tmp = (31 - lsb - 10) - tmp;
309 /* Pin connected to SDA10 is (31 - lsb - 10).
310 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
311 so (rowst + tmp) alternates with AP.
312 */
313 if (pbi) /* Table 10-7 */
314 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
315 else
316 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
317
318 /* SDRAM device-specific parameters */
319 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
320 switch (tmp) { /* RFRC */
321 case 1:
322 case 2:
323 psdmr |= (1 << 15);
324 break;
325 case 3:
326 case 4:
327 case 5:
328 case 6:
329 case 7:
330 case 8:
331 psdmr |= ((tmp - 2) << 15);
332 break;
333 default:
334 psdmr |= (7 << 15);
335 }
336 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
337 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
338 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
339 /* LDOTOPRE ??? */
340 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
341 tmp >>= 1;
342 switch (i) { /* WRC */
343 case 0:
344 case 1:
345 psdmr |= (1 << 4);
346 break;
347 case 2:
348 case 3:
349 psdmr |= (i << 4);
350 break;
351 }
352 /* EAMUX=0 - no external address multiplexing */
353 /* BUFCMD=0 - no external buffers */
354 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
355 tmp >>= 1;
356 psdmr |= i; /* CL */
357
358 switch (spd.refresh & 0x7F) {
359 case 1:
360 tmp = 3900;
361 break;
362 case 2:
363 tmp = 7800;
364 break;
365 case 3:
366 tmp = 31300;
367 break;
368 case 4:
369 tmp = 62500;
370 break;
371 case 5:
372 tmp = 125000;
373 break;
374 default:
375 tmp = 15625;
376 }
377 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
378 ((memctl->memc_mptpr >> 8) + 1)) - 1;
379 #ifdef SPD_DEBUG
380 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
381 printf ("SPD size: %d\n", spd.info_size);
382 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
383 printf ("Memory type: %d\n", spd.mem_type);
384 printf ("Row addr: %d\n", spd.nrow_addr);
385 printf ("Column addr: %d\n", spd.ncol_addr);
386 printf ("# of rows: %d\n", spd.nrows);
387 printf ("Row density: %d\n", spd.row_dens);
388 printf ("# of banks: %d\n", spd.nbanks);
389 printf ("Data width: %d\n",
390 256 * spd.dataw_msb + spd.dataw_lsb);
391 printf ("Chip width: %d\n", spd.primw);
392 printf ("Refresh rate: %02X\n", spd.refresh);
393 printf ("CAS latencies: %02X\n", spd.cas_lat);
394 printf ("Write latencies: %02X\n", spd.write_lat);
395 printf ("tRP: %d\n", spd.trp);
396 printf ("tRCD: %d\n", spd.trcd);
397
398 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
399 #endif /* SPD_DEBUG */
400 }
401 #endif /* CONFIG_SPD_EEPROM */
402 memctl->memc_psrt = psrt;
403 memctl->memc_or2 = or;
404 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
405 ramaddr = (uchar *) CFG_SDRAM_BASE;
406 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
407 *ramaddr = c;
408 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
409 for (i = 0; i < 8; i++)
410 *ramaddr = c;
411
412 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
413 *ramaddr = c;
414 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
415 *ramaddr = c;
416 #endif
417
418 /* return total ram size of DIMM */
419 return (msize * 1024 * 1024);
420 }
421
422 int checkboard (void)
423 {
424 puts ("Board: Motorola MPC8260ADS\n");
425 return 0;
426 }
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