board/mpc8540ads/mpc8540ads.c

   1  /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <asm/immap_85xx.h>
  32 #include <spd.h>
  33
  34 #if defined(CONFIG_OF_FLAT_TREE)
  35 #include <ft_build.h>
  36 #endif
  37
  38
  39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  40 extern void ddr_enable_ecc(unsigned int dram_size);
  41 #endif
  42
  43 extern long int spd_sdram(void);
  44
  45 void local_bus_init(void);
  46 void sdram_init(void);
  47 long int fixed_sdram(void);
  48
  49
  50 int board_early_init_f (void)
  51 {
  52     return 0;
  53 }
  54
  55 int checkboard (void)
  56 {
  57         puts("Board: ADS\n");
  58
  59 #ifdef CONFIG_PCI
  60         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
  61                CONFIG_SYS_CLK_FREQ / 1000000);
  62 #else
  63         printf("    PCI1: disabled\n");
  64 #endif
  65
  66         /*
  67          * Initialize local bus.
  68          */
  69         local_bus_init();
  70
  71         return 0;
  72 }
  73
  74
  75 long int
  76 initdram(int board_type)
  77 {
  78         long dram_size = 0;
  79         extern long spd_sdram (void);
  80         volatile immap_t *immap = (immap_t *)CFG_IMMR;
  81
  82         puts("Initializing\n");
  83
  84 #if defined(CONFIG_DDR_DLL)
  85         {
  86             volatile ccsr_gur_t *gur= &immap->im_gur;
  87             uint temp_ddrdll = 0;
  88
  89             /*
  90              * Work around to stabilize DDR DLL
  91              */
  92             temp_ddrdll = gur->ddrdllcr;
  93             gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  94             asm("sync;isync;msync");
  95         }
  96 #endif
  97
  98 #if defined(CONFIG_SPD_EEPROM)
  99         dram_size = spd_sdram ();
 100 #else
 101         dram_size = fixed_sdram ();
 102 #endif
 103
 104 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 105         /*
 106          * Initialize and enable DDR ECC.
 107          */
 108         ddr_enable_ecc(dram_size);
 109 #endif
 110
 111         /*
 112          * Initialize SDRAM.
 113          */
 114         sdram_init();
 115
 116         puts("    DDR: ");
 117         return dram_size;
 118 }
 119
 120
 121 /*
 122  * Initialize Local Bus
 123  */
 124
 125 void
 126 local_bus_init(void)
 127 {
 128         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 129         volatile ccsr_gur_t *gur = &immap->im_gur;
 130         volatile ccsr_lbc_t *lbc = &immap->im_lbc;
 131
 132         uint clkdiv;
 133         uint lbc_hz;
 134         sys_info_t sysinfo;
 135
 136         /*
 137          * Errata LBC11.
 138          * Fix Local Bus clock glitch when DLL is enabled.
 139          *
 140          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 141          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 142          * Between 66 and 133, the DLL is enabled with an override workaround.
 143          */
 144
 145         get_sys_info(&sysinfo);
 146         clkdiv = lbc->lcrr & 0x0f;
 147         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 148
 149         if (lbc_hz < 66) {
 150                 lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
 151
 152         } else if (lbc_hz >= 133) {
 153                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 154
 155         } else {
 156                 /*
 157                  * On REV1 boards, need to change CLKDIV before enable DLL.
 158                  * Default CLKDIV is 8, change it to 4 temporarily.
 159                  */
 160                 uint pvr = get_pvr();
 161                 uint temp_lbcdll = 0;
 162
 163                 if (pvr == PVR_85xx_REV1) {
 164                         /* FIXME: Justify the high bit here. */
 165                         lbc->lcrr = 0x10000004;
 166                 }
 167
 168                 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 169                 udelay(200);
 170
 171                 /*
 172                  * Sample LBC DLL ctrl reg, upshift it to set the
 173                  * override bits.
 174                  */
 175                 temp_lbcdll = gur->lbcdllcr;
 176                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 177                 asm("sync;isync;msync");
 178         }
 179 }
 180
 181
 182 /*
 183  * Initialize SDRAM memory on the Local Bus.
 184  */
 185
 186 void
 187 sdram_init(void)
 188 {
 189         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 190         volatile ccsr_lbc_t *lbc= &immap->im_lbc;
 191         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 192
 193         puts("    SDRAM: ");
 194         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 195
 196         /*
 197          * Setup SDRAM Base and Option Registers
 198          */
 199         lbc->or2 = CFG_OR2_PRELIM;
 200         lbc->br2 = CFG_BR2_PRELIM;
 201         lbc->lbcr = CFG_LBC_LBCR;
 202         asm("msync");
 203
 204         lbc->lsrt = CFG_LBC_LSRT;
 205         lbc->mrtpr = CFG_LBC_MRTPR;
 206         asm("sync");
 207
 208         /*
 209          * Configure the SDRAM controller.
 210          */
 211         lbc->lsdmr = CFG_LBC_LSDMR_1;
 212         asm("sync");
 213         *sdram_addr = 0xff;
 214         ppcDcbf((unsigned long) sdram_addr);
 215         udelay(100);
 216
 217         lbc->lsdmr = CFG_LBC_LSDMR_2;
 218         asm("sync");
 219         *sdram_addr = 0xff;
 220         ppcDcbf((unsigned long) sdram_addr);
 221         udelay(100);
 222
 223         lbc->lsdmr = CFG_LBC_LSDMR_3;
 224         asm("sync");
 225         *sdram_addr = 0xff;
 226         ppcDcbf((unsigned long) sdram_addr);
 227         udelay(100);
 228
 229         lbc->lsdmr = CFG_LBC_LSDMR_4;
 230         asm("sync");
 231         *sdram_addr = 0xff;
 232         ppcDcbf((unsigned long) sdram_addr);
 233         udelay(100);
 234
 235         lbc->lsdmr = CFG_LBC_LSDMR_5;
 236         asm("sync");
 237         *sdram_addr = 0xff;
 238         ppcDcbf((unsigned long) sdram_addr);
 239         udelay(100);
 240 }
 241
 242
 243 #if defined(CFG_DRAM_TEST)
 244 int testdram (void)
 245 {
 246         uint *pstart = (uint *) CFG_MEMTEST_START;
 247         uint *pend = (uint *) CFG_MEMTEST_END;
 248         uint *p;
 249
 250         printf("SDRAM test phase 1:\n");
 251         for (p = pstart; p < pend; p++)
 252                 *p = 0xaaaaaaaa;
 253
 254         for (p = pstart; p < pend; p++) {
 255                 if (*p != 0xaaaaaaaa) {
 256                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 257                         return 1;
 258                 }
 259         }
 260
 261         printf("SDRAM test phase 2:\n");
 262         for (p = pstart; p < pend; p++)
 263                 *p = 0x55555555;
 264
 265         for (p = pstart; p < pend; p++) {
 266                 if (*p != 0x55555555) {
 267                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 268                         return 1;
 269                 }
 270         }
 271
 272         printf("SDRAM test passed.\n");
 273         return 0;
 274 }
 275 #endif
 276
 277
 278 #if !defined(CONFIG_SPD_EEPROM)
 279 /*************************************************************************
 280  *  fixed sdram init -- doesn't use serial presence detect.
 281  ************************************************************************/
 282 long int fixed_sdram (void)
 283 {
 284   #ifndef CFG_RAMBOOT
 285         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 286         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 287
 288         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 289         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 290         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 291         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 292         ddr->sdram_mode = CFG_DDR_MODE;
 293         ddr->sdram_interval = CFG_DDR_INTERVAL;
 294     #if defined (CONFIG_DDR_ECC)
 295         ddr->err_disable = 0x0000000D;
 296         ddr->err_sbe = 0x00ff0000;
 297     #endif
 298         asm("sync;isync;msync");
 299         udelay(500);
 300     #if defined (CONFIG_DDR_ECC)
 301         /* Enable ECC checking */
 302         ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
 303     #else
 304         ddr->sdram_cfg = CFG_DDR_CONTROL;
 305     #endif
 306         asm("sync; isync; msync");
 307         udelay(500);
 308   #endif
 309         return CFG_SDRAM_SIZE * 1024 * 1024;
 310 }
 311 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 312
 313
 314 #if defined(CONFIG_PCI)
 315 /*
 316  * Initialize PCI Devices, report devices found.
 317  */
 318
 319
 320 static struct pci_controller hose;
 321
 322 #endif  /* CONFIG_PCI */
 323
 324
 325 void
 326 pci_init_board(void)
 327 {
 328 #ifdef CONFIG_PCI
 329         pci_mpc85xx_init(&hose);
 330 #endif /* CONFIG_PCI */
 331 }
 332
 333
 334 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 335 void
 336 ft_board_setup(void *blob, bd_t *bd)
 337 {
 338         u32 *p;
 339         int len;
 340
 341 #ifdef CONFIG_PCI
 342         ft_pci_setup(blob, bd);
 343 #endif
 344         ft_cpu_setup(blob, bd);
 345
 346         p = ft_get_prop(blob, "/memory/reg", &len);
 347         if (p != NULL) {
 348                 *p++ = cpu_to_be32(bd->bi_memstart);
 349                 *p = cpu_to_be32(bd->bi_memsize);
 350         }
 351 }
 352 #endif