board/mpc8641hpcn/init.S

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Jeff Brown
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <ppc_asm.tmpl>
  26 #include <ppc_defs.h>
  27 #include <asm/cache.h>
  28 #include <asm/mmu.h>
  29 #include <config.h>
  30 #include <mpc86xx.h>
  31
  32 /*
  33  * LAW(Local Access Window) configuration:
  34  *
  35  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  36  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  37  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
  38  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
  39  * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
  40  * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
  41  * 0xf800_0000     0xf80f_ffff     CCSRBAR                 1M
  42  * 0xf810_0000     0xf81f_ffff     PIXIS                   1M
  43  * 0xfe00_0000     0xffff_ffff     FLASH (boot bank)       32M
  44  *
  45  * Notes:
  46  *    CCSRBAR don't need a configured Local Access Window.
  47  *    If flash is 8M at default position (last 8M), no LAW needed.
  48  */
  49
  50 #if !defined(CONFIG_SPD_EEPROM)
  51 #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
  52 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
  53 #else
  54 #define LAWBAR1 0
  55 #define LAWAR1  ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
  56 #endif
  57
  58 #define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
  59 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  60
  61 #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
  62 #define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
  63
  64 /*
  65  * This is not so much the SDRAM map as it is the whole localbus map.
  66  */
  67 #define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
  68 #define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
  69
  70 #define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
  71 #define LAWAR5  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  72
  73 #define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
  74 #define LAWAR6  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
  75
  76 #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
  77 #define LAWAR7  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
  78
  79 #if !defined(CONFIG_SPD_EEPROM)
  80 #define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
  81 #define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
  82 #else
  83 #define LAWBAR8 0
  84 #define LAWAR8  ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
  85 #endif
  86
  87 #define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
  88 #define LAWAR9  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
  89
  90         .section .bootpg, "ax"
  91         .globl  law_entry
  92 law_entry:
  93         lis     r7,CFG_CCSRBAR@h
  94         ori     r7,r7,CFG_CCSRBAR@l
  95
  96         addi    r4,r7,0
  97         addi    r5,r7,0
  98
  99         /* Skip LAWAR0, start at LAWAR1 */
 100         lis     r6,LAWBAR1@h
 101         ori     r6,r6,LAWBAR1@l
 102         stwu    r6, 0xc28(r4)
 103
 104         lis     r6,LAWAR1@h
 105         ori     r6,r6,LAWAR1@l
 106         stwu    r6, 0xc30(r5)
 107
 108         /* LAWBAR2, LAWAR2 */
 109         lis     r6,LAWBAR2@h
 110         ori     r6,r6,LAWBAR2@l
 111         stwu    r6, 0x20(r4)
 112
 113         lis     r6,LAWAR2@h
 114         ori     r6,r6,LAWAR2@l
 115         stwu    r6, 0x20(r5)
 116
 117         /* LAWBAR3, LAWAR3 */
 118         lis     r6,LAWBAR3@h
 119         ori     r6,r6,LAWBAR3@l
 120         stwu    r6, 0x20(r4)
 121
 122         lis     r6,LAWAR3@h
 123         ori     r6,r6,LAWAR3@l
 124         stwu    r6, 0x20(r5)
 125
 126         /* LAWBAR4, LAWAR4 */
 127         lis     r6,LAWBAR4@h
 128         ori     r6,r6,LAWBAR4@l
 129         stwu    r6, 0x20(r4)
 130
 131         lis     r6,LAWAR4@h
 132         ori     r6,r6,LAWAR4@l
 133         stwu    r6, 0x20(r5)
 134         /* LAWBAR5, LAWAR5 */
 135         lis     r6,LAWBAR5@h
 136         ori     r6,r6,LAWBAR5@l
 137         stwu    r6, 0x20(r4)
 138
 139         lis     r6,LAWAR5@h
 140         ori     r6,r6,LAWAR5@l
 141         stwu    r6, 0x20(r5)
 142
 143         /* LAWBAR6, LAWAR6 */
 144         lis     r6,LAWBAR6@h
 145         ori     r6,r6,LAWBAR6@l
 146         stwu    r6, 0x20(r4)
 147
 148         lis     r6,LAWAR6@h
 149         ori     r6,r6,LAWAR6@l
 150         stwu    r6, 0x20(r5)
 151
 152         /* LAWBAR7, LAWAR7 */
 153         lis     r6,LAWBAR7@h
 154         ori     r6,r6,LAWBAR7@l
 155         stwu    r6, 0x20(r4)
 156
 157         lis     r6,LAWAR7@h
 158         ori     r6,r6,LAWAR7@l
 159         stwu    r6, 0x20(r5)
 160
 161         /* LAWBAR8, LAWAR8 */
 162         lis     r6,LAWBAR8@h
 163         ori     r6,r6,LAWBAR8@l
 164         stwu    r6, 0x20(r4)
 165
 166         lis     r6,LAWAR8@h
 167         ori     r6,r6,LAWAR8@l
 168         stwu    r6, 0x20(r5)
 169
 170         /* LAWBAR9, LAWAR9 */
 171         lis     r6,LAWBAR9@h
 172         ori     r6,r6,LAWBAR9@l
 173         stwu    r6, 0x20(r4)
 174
 175         lis     r6,LAWAR9@h
 176         ori     r6,r6,LAWAR9@l
 177         stwu    r6, 0x20(r5)
 178
 179         blr