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git.ipfire.org Git - people/ms/u-boot.git/blob - board/mpl/pati/cmd_pati.c
3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include "pci_eeprom.h"
33 extern void show_pld_regs(void);
34 extern int do_mplcommon(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[]);
36 extern void user_led0(int led_on
);
37 extern void user_led1(int led_on
);
39 /* ------------------------------------------------------------------------- */
40 #if defined(CFG_PCI_CON_DEVICE)
41 extern void pci_con_disc(void);
42 extern void pci_con_connect(void);
45 /******************************************************************************
47 ******************************************************************************/
48 unsigned long get32(unsigned long addr
)
50 unsigned long *p
=(unsigned long *)addr
;
54 void set32(unsigned long addr
,unsigned long data
)
56 unsigned long *p
=(unsigned long *)addr
;
60 #define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE))
61 #define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y)))
64 /******************************************************************************
66 ******************************************************************************/
68 static void reload_pci_eeprom(void)
71 /* Set Bit 29 and clear it again */
72 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
76 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
77 /* EECLK @ 33MHz = 125kHz
78 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
81 udelay(20000); /* wait 20ms */
82 reg
&= ~(1<<29); /* set it low */
83 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
84 udelay(1); /* wait some time */
87 /******************************************************************************
89 ******************************************************************************/
91 static void clock_pci_eeprom(void)
94 /* clock is low, data is valid */
95 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
99 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
100 udelay(1); /* wait some time */
101 reg
&= ~(1<<24); /* set clock low */
102 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
103 udelay(1); /* wait some time */
106 /******************************************************************************
107 * send_pci_eeprom_cmd
108 ******************************************************************************/
109 static void send_pci_eeprom_cmd(unsigned long cmd
, unsigned char len
)
113 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
114 /* Clear all EEPROM bits */
116 /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
117 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
118 udelay(1); /* wait some time */
119 /* Enable EEPROM Chip Select */
121 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
122 /* Send EEPROM command - one bit at a time */
123 for (i
= (int)(len
-1); i
>= 0; i
--) {
124 /* Check if current bit is 0 or 1 */
126 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,(reg
| (1<<26)));
128 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
133 /******************************************************************************
134 * write_pci_eeprom_offs
135 ******************************************************************************/
136 static void write_pci_eeprom_offs(unsigned short offset
, unsigned short value
)
139 int bitpos
, cmdshft
, cmdlen
, timeout
;
140 /* we're using the Eeprom 93CS66 */
142 cmdlen
= EE66_CMD_LEN
;
143 /* Send Write_Enable command to EEPROM */
144 send_pci_eeprom_cmd((EE_WREN
<< cmdshft
),cmdlen
);
145 /* Send EEPROM Write command and offset to EEPROM */
146 send_pci_eeprom_cmd((EE_WRITE
<< cmdshft
) | (offset
/ 2),cmdlen
);
147 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
148 /* Clear all EEPROM bits */
150 /* Make sure EEDO Input is disabled for some PLX chips */
152 /* Enable EEPROM Chip Select */
154 /* Write 16-bit value to EEPROM - one bit at a time */
155 for (bitpos
= 15; bitpos
>= 0; bitpos
--) {
156 /* Get bit value and shift into result */
157 if (value
& (1 << bitpos
))
158 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,(reg
| (1<<26)));
160 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
);
164 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(1 << 25));
166 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
| (1 << 25));
167 /* A small delay is needed to let EEPROM complete */
171 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
173 } while (((reg
& (1 << 27)) == 0) && timeout
< 20000);
174 /* Send Write_Disable command to EEPROM */
175 send_pci_eeprom_cmd((EE_WDS
<< cmdshft
),cmdlen
);
176 /* Clear Chip Select and all other EEPROM bits */
177 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(0xF << 24));
181 /******************************************************************************
182 * read_pci_eeprom_offs
183 ******************************************************************************/
184 static void read_pci_eeprom_offs(unsigned short offset
, unsigned short *pvalue
)
187 int bitpos
, cmdshft
, cmdlen
;
188 /* we're using the Eeprom 93CS66 */
190 cmdlen
= EE66_CMD_LEN
;
191 /* Send EEPROM read command and offset to EEPROM */
192 send_pci_eeprom_cmd((EE_READ
<< cmdshft
) | (offset
/ 2),cmdlen
);
193 /* Set EEPROM write output bit */
194 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
195 /* Set EEDO Input enable */
197 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
| (1 << 26));
198 /* Get 16-bit value from EEPROM - one bit at a time */
199 for (bitpos
= 0; bitpos
< 16; bitpos
++) {
202 reg
=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
);
203 /* Get bit value and shift into result */
205 *pvalue
= (unsigned short)((*pvalue
<< 1) | 1);
207 *pvalue
= (unsigned short)(*pvalue
<< 1);
209 /* Clear EEDO Input enable */
211 /* Clear Chip Select and all other EEPROM bits */
212 PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT
,reg
& ~(0xF << 24));
216 /******************************************************************************
218 ******************************************************************************/
221 static int pati_pci_eeprom_erase(void)
224 printf("Erasing EEPROM ");
225 for( i
=0; i
< PATI_EEPROM_LAST_OFFSET
; i
+=2) {
226 write_pci_eeprom_offs(i
,0xffff);
234 static int pati_pci_eeprom_prg(void)
238 printf("Programming EEPROM ");
239 while(pati_eeprom
[i
].offset
<0xffff) {
240 write_pci_eeprom_offs(pati_eeprom
[i
].offset
,pati_eeprom
[i
].value
);
242 printf("0x%04X: 0x%04X\n",pati_eeprom
[i
].offset
, pati_eeprom
[i
].value
);
253 static int pati_pci_eeprom_write(unsigned short offset
, unsigned long addr
, unsigned short size
)
256 unsigned short value
;
257 unsigned short *buffer
=(unsigned short *)addr
;
258 if((offset
+ size
) > PATI_EEPROM_LAST_OFFSET
) {
259 size
= PATI_EEPROM_LAST_OFFSET
- offset
;
261 printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr
, offset
, size
/2);
262 for( i
= offset
; i
< (offset
+ size
); i
+=2) {
264 write_pci_eeprom_offs(i
,value
);
266 printf("0x%04X: 0x%04X\n",i
, value
);
276 static int pati_pci_eeprom_read(unsigned short offset
, unsigned long addr
, unsigned short size
)
279 unsigned short value
;
280 unsigned short *buffer
=(unsigned short *)addr
;
281 if((offset
+ size
) > PATI_EEPROM_LAST_OFFSET
) {
282 size
= PATI_EEPROM_LAST_OFFSET
- offset
;
284 printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset
, addr
, size
/2);
285 for( i
= offset
; i
< (offset
+ size
); i
+=2) {
286 read_pci_eeprom_offs(i
,&value
);
289 printf("0x%04X: 0x%04X\n",i
, value
);
299 /******************************************************************************
300 * PCI Bridge Registers Dump
301 *******************************************************************************/
302 static void display_pci_regs(void)
304 printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE
));
305 printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP
));
306 printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT
));
307 printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC
));
308 printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE
));
309 printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP
));
310 printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC
));
311 printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE
));
312 printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE
));
313 printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE
));
314 printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP
));
315 printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG
));
316 printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE
));
317 printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP
));
318 printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC
));
319 printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC
));
320 printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0
));
321 printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1
));
322 printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2
));
323 printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3
));
324 printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4
));
325 printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5
));
326 printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6
));
327 printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7
));
328 printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL
));
329 printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL
));
330 printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT
));
331 printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT
));
332 printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID
));
333 printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID
));
335 printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID
));
336 printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND
));
337 printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION
));
338 printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE
));
339 printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE
));
340 printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE
));
341 printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0
));
342 printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1
));
343 printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1
));
344 printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2
));
345 printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR
));
346 printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID
));
347 printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE
));
348 printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR
));
349 printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE
));
350 printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID
));
351 printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR
));
352 printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID
));
353 printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID
));
354 printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA
));
358 int do_pati(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
360 if (strcmp(argv
[1], "info") == 0)
365 if (strcmp(argv
[1], "pci") == 0)
370 if (strcmp(argv
[1], "led") == 0)
373 led_nr
= (int)simple_strtoul(argv
[2], NULL
, 10);
374 led_on
= (int)simple_strtoul(argv
[3], NULL
, 10);
381 #if defined(CFG_PCI_CON_DEVICE)
382 if (strcmp(argv
[1], "con") == 0) {
386 if (strcmp(argv
[1], "disc") == 0) {
391 if (strcmp(argv
[1], "eeprom") == 0) {
395 size
= PATI_EEPROM_LAST_OFFSET
;
398 addr
= simple_strtoul(argv
[3], NULL
, 16);
400 offset
= (int) simple_strtoul(argv
[4], NULL
, 16);
402 size
= (int) simple_strtoul(argv
[5], NULL
, 16);
403 if (strcmp(argv
[2], "read") == 0) {
404 return (pati_pci_eeprom_read(offset
, addr
, size
));
406 if (strcmp(argv
[2], "write") == 0) {
407 return (pati_pci_eeprom_write(offset
, addr
, size
));
410 if (strcmp(argv
[2], "prg") == 0) {
411 return (pati_pci_eeprom_prg());
413 if (strcmp(argv
[2], "era") == 0) {
414 return (pati_pci_eeprom_erase());
416 if (strcmp(argv
[2], "reload") == 0) {
425 return (do_mplcommon(cmdtp
, flag
, argc
, argv
));
430 "pati - PATI specific Cmds\n",
431 "info - displays board information\n"
432 "pati pci - displays PCI registers\n"
433 "pati led <nr> <on> \n"
434 " - switch LED <nr> <on>\n"
435 "pati flash mem [SrcAddr]\n"
436 " - updates U-Boot with image in memory\n"
437 "pati eeprom <cmd> - PCI EEPROM sub-system\n"
438 " read <addr> <offset> <size>\n"
439 " - read PCI EEPROM to <addr> from <offset> <size> words\n"
440 " write <addr> <offset> <size>\n"
441 " - write PCI EEPROM from <addr> to <offset> <size> words\n"
442 " prg - programm PCI EEPROM with default values\n"
443 " era - erase PCI EEPROM (write all word to 0xffff)\n"
444 " reload- Reload PCI Bridge with EEPROM Values\n"
445 " NOTE: <addr> must start on word boundary\n"
446 " <offset> and <size> must be even byte values\n"
449 /* ------------------------------------------------------------------------- */