3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 #include <stdio_dev.h>
32 #include "../common/isa.h"
33 #include "../common/common_util.h"
35 DECLARE_GLOBAL_DATA_PTR
;
42 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
43 #ifndef __ldiv_t_defined
45 long int quot
; /* Quotient */
46 long int rem
; /* Remainder */
48 extern ldiv_t ldiv (long int __numer
, long int __denom
);
50 # define __ldiv_t_defined 1
58 SDRAM_UNSUPPORTED_ERR
,
63 const unsigned char mode
;
64 const unsigned char row
;
65 const unsigned char col
;
66 const unsigned char bank
;
69 static const SDRAM_SETUP sdram_setup_table
[] = {
88 static const unsigned char cal_indextable
[] = {
94 * translate ns.ns/10 coding of SPD timing values
95 * into 10 ps unit values
98 unsigned short NS10to10PS (unsigned char spd_byte
, unsigned char spd_version
)
100 unsigned short ns
, ns10
;
102 /* isolate upper nibble */
103 ns
= (spd_byte
>> 4) & 0x0F;
104 /* isolate lower nibble */
105 ns10
= (spd_byte
& 0x0F);
107 return (ns
* 100 + ns10
* 10);
111 * translate ns.ns/4 coding of SPD timing values
112 * into 10 ps unit values
115 unsigned short NS4to10PS (unsigned char spd_byte
, unsigned char spd_version
)
117 unsigned short ns
, ns4
;
119 /* isolate upper 6 bits */
120 ns
= (spd_byte
>> 2) & 0x3F;
121 /* isloate lower 2 bits */
122 ns4
= (spd_byte
& 0x03);
124 return (ns
* 100 + ns4
* 25);
128 * translate ns coding of SPD timing values
129 * into 10 ps unit values
132 unsigned short NSto10PS (unsigned char spd_byte
)
134 return (spd_byte
* 100);
137 void SDRAM_err (const char *s
)
140 (void) get_clocks ();
146 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
153 void write_hex (unsigned char i
)
160 serial_putc (cc
+ 55);
162 serial_putc (cc
+ 48);
165 serial_putc (cc
+ 55);
167 serial_putc (cc
+ 48);
170 void write_4hex (unsigned long val
)
172 write_hex ((unsigned char) (val
>> 24));
173 write_hex ((unsigned char) (val
>> 16));
174 write_hex ((unsigned char) (val
>> 8));
175 write_hex ((unsigned char) val
);
180 int board_early_init_f (void)
182 unsigned char dataout
[1];
183 unsigned char datain
[128];
184 unsigned long sdram_size
= 0;
185 SDRAM_SETUP
*t
= (SDRAM_SETUP
*) sdram_setup_table
;
186 unsigned long memclk
;
187 unsigned long tmemclk
= 0;
188 unsigned long tmp
, bank
, baseaddr
, bank_size
;
190 unsigned char rows
, cols
, banks
, sdram_banks
, density
;
191 unsigned char supported_cal
, trp_clocks
, trcd_clocks
, tras_clocks
,
192 trc_clocks
, tctp_clocks
;
193 unsigned char cal_index
, cal_val
, spd_version
, spd_chksum
;
194 unsigned char buf
[8];
195 /* set up the config port */
196 mtdcr (EBC0_CFGADDR
, PB7AP
);
197 mtdcr (EBC0_CFGDATA
, CONFIG_PORT_AP
);
198 mtdcr (EBC0_CFGADDR
, PB7CR
);
199 mtdcr (EBC0_CFGDATA
, CONFIG_PORT_CR
);
201 memclk
= get_bus_freq (tmemclk
);
202 tmemclk
= 1000000000 / (memclk
/ 100); /* in 10 ps units */
205 (void) get_clocks ();
208 serial_puts ("\nstart SDRAM Setup\n");
211 /* Read Serial Presence Detect Information */
212 i2c_init (CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
214 for (i
= 0; i
< 128; i
++)
216 i2c_read(SPD_EEPROM_ADDRESS
,0,1,datain
,128);
218 serial_puts ("\ni2c_read returns ");
224 for (i
= 0; i
< 128; i
++) {
225 write_hex (datain
[i
]);
227 if (((i
+ 1) % 16) == 0)
233 for (i
= 0; i
< 63; i
++) {
234 spd_chksum
+= datain
[i
];
236 if (datain
[63] != spd_chksum
) {
238 serial_puts ("SPD chksum: 0x");
239 write_hex (datain
[63]);
240 serial_puts (" != calc. chksum: 0x");
241 write_hex (spd_chksum
);
244 SDRAM_err ("SPD checksum Error");
246 /* SPD seems to be ok, use it */
248 /* get SPD version */
249 spd_version
= datain
[62];
251 /* do some sanity checks on the kind of RAM */
252 if ((datain
[0] < 0x80) || /* less than 128 valid bytes in SPD */
253 (datain
[2] != 0x04) || /* if not SDRAM */
254 (!((datain
[6] == 0x40) || (datain
[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
255 (datain
[7] != 0x00) || (datain
[8] != 0x01) || /* or not LVTTL signal levels */
256 (datain
[126] == 0x66)) /* or a 66MHz modules */
257 SDRAM_err ("unsupported SDRAM");
259 serial_puts ("SDRAM sanity ok\n");
262 /* get number of rows/cols/banks out of byte 3+4+5 */
267 /* get number of SDRAM banks out of byte 17 and
268 supported CAS latencies out of byte 18 */
269 sdram_banks
= datain
[17];
270 supported_cal
= datain
[18] & ~0x81;
272 while (t
->mode
!= 0) {
273 if ((t
->row
== rows
) && (t
->col
== cols
)
274 && (t
->bank
== sdram_banks
))
280 serial_puts ("rows: ");
282 serial_puts (" cols: ");
284 serial_puts (" banks: ");
286 serial_puts (" mode: ");
291 SDRAM_err ("unsupported SDRAM");
292 /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
294 serial_puts ("tRP: ");
295 write_hex (datain
[27]);
296 serial_puts ("\ntRCD: ");
297 write_hex (datain
[29]);
298 serial_puts ("\ntRAS: ");
299 write_hex (datain
[30]);
303 trp_clocks
= (NSto10PS (datain
[27]) + (tmemclk
- 1)) / tmemclk
;
304 trcd_clocks
= (NSto10PS (datain
[29]) + (tmemclk
- 1)) / tmemclk
;
305 tras_clocks
= (NSto10PS (datain
[30]) + (tmemclk
- 1)) / tmemclk
;
306 density
= datain
[31];
308 /* trc_clocks is sum of trp_clocks + tras_clocks */
309 trc_clocks
= trp_clocks
+ tras_clocks
;
310 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
312 ((NSto10PS (datain
[30]) - NSto10PS (datain
[29])) +
313 (tmemclk
- 1)) / tmemclk
;
316 serial_puts ("c_RP: ");
317 write_hex (trp_clocks
);
318 serial_puts ("\nc_RCD: ");
319 write_hex (trcd_clocks
);
320 serial_puts ("\nc_RAS: ");
321 write_hex (tras_clocks
);
322 serial_puts ("\nc_RC: (RP+RAS): ");
323 write_hex (trc_clocks
);
324 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
325 write_hex (tctp_clocks
);
326 serial_puts ("\nt_CTP: RAS - RCD: ");
328 char) ((NSto10PS (datain
[30]) -
329 NSto10PS (datain
[29])) >> 8));
330 write_hex ((unsigned char) (NSto10PS (datain
[30]) - NSto10PS (datain
[29])));
331 serial_puts ("\ntmemclk: ");
332 write_hex ((unsigned char) (tmemclk
>> 8));
333 write_hex ((unsigned char) (tmemclk
));
339 for (i
= 6, cal_index
= 0; (i
> 0) && (cal_index
< 3); i
--) {
340 /* is this CAS latency supported ? */
341 if ((supported_cal
>> i
) & 0x01) {
342 buf
[0] = datain
[cal_indextable
[cal_index
]];
344 if (NS10to10PS (buf
[0], spd_version
) <= tmemclk
)
347 /* SPD bytes 25+26 have another format */
348 if (NS4to10PS (buf
[0], spd_version
) <= tmemclk
)
355 serial_puts ("CAL: ");
356 write_hex (cal_val
+ 1);
361 SDRAM_err ("unsupported SDRAM");
363 /* get SDRAM timing register */
364 mtdcr (SDRAM0_CFGADDR
, mem_sdtr1
);
365 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x018FC01F;
366 /* insert CASL value */
367 /* tmp |= ((unsigned long)cal_val) << 23; */
368 tmp
|= ((unsigned long) cal_val
) << 23;
369 /* insert PTA value */
370 tmp
|= ((unsigned long) (trp_clocks
- 1)) << 18;
371 /* insert CTP value */
372 /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
373 tmp
|= ((unsigned long) (trc_clocks
- trp_clocks
- trcd_clocks
)) << 16;
374 /* insert LDF (always 01) */
375 tmp
|= ((unsigned long) 0x01) << 14;
376 /* insert RFTA value */
377 tmp
|= ((unsigned long) (trc_clocks
- 4)) << 2;
378 /* insert RCD value */
379 tmp
|= ((unsigned long) (trcd_clocks
- 1)) << 0;
382 serial_puts ("sdtr: ");
387 /* write SDRAM timing register */
388 mtdcr (SDRAM0_CFGADDR
, mem_sdtr1
);
389 mtdcr (SDRAM0_CFGDATA
, tmp
);
390 baseaddr
= CONFIG_SYS_SDRAM_BASE
;
391 bank_size
= (((unsigned long) density
) << 22) / 2;
392 /* insert AM value */
393 tmp
= ((unsigned long) t
->mode
- 1) << 13;
394 /* insert SZ value; */
397 tmp
|= ((unsigned long) 0x00) << 17;
400 tmp
|= ((unsigned long) 0x01) << 17;
403 tmp
|= ((unsigned long) 0x02) << 17;
406 tmp
|= ((unsigned long) 0x03) << 17;
409 tmp
|= ((unsigned long) 0x04) << 17;
412 tmp
|= ((unsigned long) 0x05) << 17;
415 tmp
|= ((unsigned long) 0x06) << 17;
418 SDRAM_err ("unsupported SDRAM");
420 /* get SDRAM bank 0 register */
421 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
422 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
423 bank
|= (baseaddr
| tmp
| 0x01);
425 serial_puts ("bank0: baseaddr: ");
426 write_4hex (baseaddr
);
427 serial_puts (" banksize: ");
428 write_4hex (bank_size
);
429 serial_puts (" mb0cf: ");
433 baseaddr
+= bank_size
;
434 sdram_size
+= bank_size
;
436 /* write SDRAM bank 0 register */
437 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
438 mtdcr (SDRAM0_CFGDATA
, bank
);
440 /* get SDRAM bank 1 register */
441 mtdcr (SDRAM0_CFGADDR
, mem_mb1cf
);
442 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
446 serial_puts ("bank1: baseaddr: ");
447 write_4hex (baseaddr
);
448 serial_puts (" banksize: ");
449 write_4hex (bank_size
);
452 bank
|= (baseaddr
| tmp
| 0x01);
453 baseaddr
+= bank_size
;
454 sdram_size
+= bank_size
;
457 serial_puts (" mb1cf: ");
461 /* write SDRAM bank 1 register */
462 mtdcr (SDRAM0_CFGADDR
, mem_mb1cf
);
463 mtdcr (SDRAM0_CFGDATA
, bank
);
465 /* get SDRAM bank 2 register */
466 mtdcr (SDRAM0_CFGADDR
, mem_mb2cf
);
467 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
469 bank
|= (baseaddr
| tmp
| 0x01);
472 serial_puts ("bank2: baseaddr: ");
473 write_4hex (baseaddr
);
474 serial_puts (" banksize: ");
475 write_4hex (bank_size
);
476 serial_puts (" mb2cf: ");
481 baseaddr
+= bank_size
;
482 sdram_size
+= bank_size
;
484 /* write SDRAM bank 2 register */
485 mtdcr (SDRAM0_CFGADDR
, mem_mb2cf
);
486 mtdcr (SDRAM0_CFGDATA
, bank
);
488 /* get SDRAM bank 3 register */
489 mtdcr (SDRAM0_CFGADDR
, mem_mb3cf
);
490 bank
= mfdcr (SDRAM0_CFGDATA
) & ~0xFFCEE001;
493 serial_puts ("bank3: baseaddr: ");
494 write_4hex (baseaddr
);
495 serial_puts (" banksize: ");
496 write_4hex (bank_size
);
500 bank
|= (baseaddr
| tmp
| 0x01);
501 baseaddr
+= bank_size
;
502 sdram_size
+= bank_size
;
506 serial_puts (" mb3cf: ");
511 /* write SDRAM bank 3 register */
512 mtdcr (SDRAM0_CFGADDR
, mem_mb3cf
);
513 mtdcr (SDRAM0_CFGDATA
, bank
);
516 /* get SDRAM refresh interval register */
517 mtdcr (SDRAM0_CFGADDR
, mem_rtr
);
518 tmp
= mfdcr (SDRAM0_CFGDATA
) & ~0x3FF80000;
520 if (tmemclk
< NSto10PS (16))
525 /* write SDRAM refresh interval register */
526 mtdcr (SDRAM0_CFGADDR
, mem_rtr
);
527 mtdcr (SDRAM0_CFGDATA
, tmp
);
529 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
530 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
531 tmp
= (mfdcr (SDRAM0_CFGDATA
) & ~0xFFE00000) | 0x80E00000;
532 mtdcr (SDRAM0_CFGADDR
, mem_mcopt1
);
533 mtdcr (SDRAM0_CFGDATA
, tmp
);
536 /*-------------------------------------------------------------------------+
537 | Interrupt controller setup for the PIP405 board.
538 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
539 | IRQ 16 405GP internally generated; active low; level sensitive
541 | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
542 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
543 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
544 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
545 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
546 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
547 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
548 | Note for PIP405 board:
549 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
550 | the Interrupt Controller in the South Bridge has caused the
551 | interrupt. The IC must be read to determine which device
552 | caused the interrupt.
554 +-------------------------------------------------------------------------*/
555 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
556 mtdcr (uicer
, 0x00000000); /* disable all ints */
557 mtdcr (uiccr
, 0x00000000); /* set all to be non-critical (for now) */
558 mtdcr (uicpr
, 0xFFFFFF80); /* set int polarities */
559 mtdcr (uictr
, 0x10000000); /* set int trigger levels */
560 mtdcr (uicvcr
, 0x00000001); /* set vect base=0,INT0 highest priority */
561 mtdcr (uicsr
, 0xFFFFFFFF); /* clear all ints */
567 /* ------------------------------------------------------------------------- */
570 * Check Board Identity:
573 int checkboard (void)
578 backup_t
*b
= (backup_t
*) s
;
582 i
= getenv_r ("serial#", (char *)s
, 32);
583 if ((i
== 0) || strncmp ((char *)s
, "PIP405", 6)) {
584 get_backup_values (b
);
585 if (strncmp (b
->signature
, "MPL\0", 4) != 0) {
586 puts ("### No HW ID - assuming PIP405");
588 b
->serial_name
[6] = 0;
589 printf ("%s SN: %s", b
->serial_name
,
594 printf ("%s SN: %s", s
, &s
[7]);
596 bc
= in8 (CONFIG_PORT_ADDR
);
597 printf (" Boot Config: 0x%x\n", bc
);
602 /* ------------------------------------------------------------------------- */
603 /* ------------------------------------------------------------------------- */
605 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
606 the necessary info for SDRAM controller configuration
608 /* ------------------------------------------------------------------------- */
609 /* ------------------------------------------------------------------------- */
610 static int test_dram (unsigned long ramsize
);
612 phys_size_t
initdram (int board_type
)
614 unsigned long bank_reg
[4], tmp
, bank_size
;
616 unsigned long TotalSize
;
619 /* since the DRAM controller is allready set up,
620 * calculate the size with the bank registers
622 mtdcr (SDRAM0_CFGADDR
, mem_mb0cf
);
623 bank_reg
[0] = mfdcr (SDRAM0_CFGDATA
);
624 mtdcr (SDRAM0_CFGADDR
, mem_mb1cf
);
625 bank_reg
[1] = mfdcr (SDRAM0_CFGDATA
);
626 mtdcr (SDRAM0_CFGADDR
, mem_mb2cf
);
627 bank_reg
[2] = mfdcr (SDRAM0_CFGDATA
);
628 mtdcr (SDRAM0_CFGADDR
, mem_mb3cf
);
629 bank_reg
[3] = mfdcr (SDRAM0_CFGDATA
);
631 for (i
= 0; i
< 4; i
++) {
632 if ((bank_reg
[i
] & 0x1) == 0x1) {
633 tmp
= (bank_reg
[i
] >> 17) & 0x7;
634 bank_size
= 4 << tmp
;
635 TotalSize
+= bank_size
;
640 printf ("single-sided DIMM ");
642 printf ("double-sided DIMM ");
643 test_dram (TotalSize
* 1024 * 1024);
644 /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
646 if (gd
->cpu_clk
> 220000000)
648 return (TotalSize
* 1024 * 1024);
651 /* ------------------------------------------------------------------------- */
654 static int test_dram (unsigned long ramsize
)
656 /* not yet implemented */
661 extern flash_info_t flash_info
[]; /* info for FLASH chips */
663 int misc_init_r (void)
665 /* adjust flash start and size as well as the offset */
666 gd
->bd
->bi_flashstart
=0-flash_info
[0].size
;
667 gd
->bd
->bi_flashsize
=flash_info
[0].size
-CONFIG_SYS_MONITOR_LEN
;
668 gd
->bd
->bi_flashoffset
=0;
670 /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
671 if (mfdcr(CPC0_PSR
) & PSR_ROM_LOC
)
672 mtspr(SPRN_CCR0
, (mfspr(SPRN_CCR0
) & ~0x80));
677 /***************************************************************************
678 * some helping routines
681 int overwrite_console (void)
683 return (in8 (CONFIG_PORT_ADDR
) & 0x1); /* return TRUE if console should be overwritten */
687 extern int isa_init (void);
690 void print_pip405_rev (void)
692 unsigned char part
, vers
, cfg
;
694 part
= in8 (PLD_PART_REG
);
695 vers
= in8 (PLD_VERS_REG
);
696 cfg
= in8 (PLD_BOARD_CFG_REG
);
697 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
698 16 - ((cfg
>> 4) & 0xf), (cfg
& 0xf) + 'A', part
& 0xf,
699 vers
& 0xf, (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
702 extern void check_env(void);
705 int last_stage_init (void)
709 stdio_print_current_devices ();
714 /************************************************************************
716 ************************************************************************/
717 void print_pip405_info (void)
719 unsigned char part
, vers
, cfg
, ledu
, sysman
, flashcom
, can
, serpwr
,
720 compwr
, nicvga
, scsirst
;
722 part
= in8 (PLD_PART_REG
);
723 vers
= in8 (PLD_VERS_REG
);
724 cfg
= in8 (PLD_BOARD_CFG_REG
);
725 ledu
= in8 (PLD_LED_USER_REG
);
726 sysman
= in8 (PLD_SYS_MAN_REG
);
727 flashcom
= in8 (PLD_FLASH_COM_REG
);
728 can
= in8 (PLD_CAN_REG
);
729 serpwr
= in8 (PLD_SER_PWR_REG
);
730 compwr
= in8 (PLD_COM_PWR_REG
);
731 nicvga
= in8 (PLD_NIC_VGA_REG
);
732 scsirst
= in8 (PLD_SCSI_RST_REG
);
733 printf ("PLD Part %d version %d\n",
734 part
& 0xf, vers
& 0xf);
735 printf ("PLD Part %d version %d\n",
736 (part
>> 4) & 0xf, (vers
>> 4) & 0xf);
737 printf ("Board Revision %c\n", (cfg
& 0xf) + 'A');
738 printf ("Population Options %d %d %d %d\n",
739 (cfg
>> 4) & 0x1, (cfg
>> 5) & 0x1,
740 (cfg
>> 6) & 0x1, (cfg
>> 7) & 0x1);
741 printf ("User LED0 %s User LED1 %s\n",
742 ((ledu
& 0x1) == 0x1) ? "on" : "off",
743 ((ledu
& 0x2) == 0x2) ? "on" : "off");
744 printf ("Additionally Options %d %d\n",
745 (ledu
>> 2) & 0x1, (ledu
>> 3) & 0x1);
746 printf ("User Config Switch %d %d %d %d\n",
747 (ledu
>> 4) & 0x1, (ledu
>> 5) & 0x1,
748 (ledu
>> 6) & 0x1, (ledu
>> 7) & 0x1);
749 switch (sysman
& 0x3) {
751 printf ("PCI Clocks are running\n");
754 printf ("PCI Clocks are stopped in POS State\n");
757 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
760 printf ("PCI Clocks are stopped\n");
763 switch ((sysman
>> 2) & 0x3) {
765 printf ("Main Clocks are running\n");
768 printf ("Main Clocks are stopped in POS State\n");
772 printf ("PCI Clocks are stopped\n");
775 printf ("INIT asserts %sINT2# (SMI)\n",
776 ((sysman
& 0x10) == 0x10) ? "" : "not ");
777 printf ("INIT asserts %sINT1# (NMI)\n",
778 ((sysman
& 0x20) == 0x20) ? "" : "not ");
779 printf ("INIT occured %d\n", (sysman
>> 6) & 0x1);
780 printf ("SER1 is routed to %s\n",
781 ((flashcom
& 0x1) == 0x1) ? "RS485" : "RS232");
782 printf ("COM2 is routed to %s\n",
783 ((flashcom
& 0x2) == 0x2) ? "RS485" : "RS232");
784 printf ("RS485 is configured as %s duplex\n",
785 ((flashcom
& 0x4) == 0x4) ? "full" : "half");
786 printf ("RS485 is connected to %s\n",
787 ((flashcom
& 0x8) == 0x8) ? "COM1" : "COM2");
788 printf ("SER1 uses handshakes %s\n",
789 ((flashcom
& 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
790 printf ("Bootflash is %swriteprotected\n",
791 ((flashcom
& 0x20) == 0x20) ? "not " : "");
792 printf ("Bootflash VPP is %s\n",
793 ((flashcom
& 0x40) == 0x40) ? "on" : "off");
794 printf ("Bootsector is %swriteprotected\n",
795 ((flashcom
& 0x80) == 0x80) ? "not " : "");
796 switch ((can
) & 0x3) {
798 printf ("CAN Controller is on address 0x1000..0x10FF\n");
801 printf ("CAN Controller is on address 0x8000..0x80FF\n");
804 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
807 printf ("CAN Controller is disabled\n");
810 switch ((can
>> 2) & 0x3) {
812 printf ("CAN Controller Reset is ISA Reset\n");
815 printf ("CAN Controller Reset is ISA Reset and POS State\n");
819 printf ("CAN Controller is in reset\n");
822 if (((can
>> 4) < 3) || ((can
>> 4) == 8) || ((can
>> 4) == 13))
823 printf ("CAN Interrupt is disabled\n");
825 printf ("CAN Interrupt is ISA INT%d\n", (can
>> 4) & 0xf);
826 switch (serpwr
& 0x3) {
828 printf ("SER0 Drivers are enabled\n");
831 printf ("SER0 Drivers are disabled in the POS state\n");
835 printf ("SER0 Drivers are disabled\n");
838 switch ((serpwr
>> 2) & 0x3) {
840 printf ("SER1 Drivers are enabled\n");
843 printf ("SER1 Drivers are disabled in the POS state\n");
847 printf ("SER1 Drivers are disabled\n");
850 switch (compwr
& 0x3) {
852 printf ("COM1 Drivers are enabled\n");
855 printf ("COM1 Drivers are disabled in the POS state\n");
859 printf ("COM1 Drivers are disabled\n");
862 switch ((compwr
>> 2) & 0x3) {
864 printf ("COM2 Drivers are enabled\n");
867 printf ("COM2 Drivers are disabled in the POS state\n");
871 printf ("COM2 Drivers are disabled\n");
874 switch ((nicvga
) & 0x3) {
876 printf ("PHY is running\n");
879 printf ("PHY is in Power save mode in POS state\n");
883 printf ("PHY is in Power save mode\n");
886 switch ((nicvga
>> 2) & 0x3) {
888 printf ("VGA is running\n");
891 printf ("VGA is in Power save mode in POS state\n");
895 printf ("VGA is in Power save mode\n");
898 printf ("PHY is %sreseted\n", ((nicvga
& 0x10) == 0x10) ? "" : "not ");
899 printf ("VGA is %sreseted\n", ((nicvga
& 0x20) == 0x20) ? "" : "not ");
900 printf ("Reserved Configuration is %d %d\n", (nicvga
>> 6) & 0x1,
901 (nicvga
>> 7) & 0x1);
902 switch ((scsirst
) & 0x3) {
904 printf ("SCSI Controller is running\n");
907 printf ("SCSI Controller is in Power save mode in POS state\n");
911 printf ("SCSI Controller is in Power save mode\n");
914 printf ("SCSI termination is %s\n",
915 ((scsirst
& 0x4) == 0x4) ? "disabled" : "enabled");
916 printf ("SCSI Controller is %sreseted\n",
917 ((scsirst
& 0x10) == 0x10) ? "" : "not ");
918 printf ("IDE disks are %sreseted\n",
919 ((scsirst
& 0x20) == 0x20) ? "" : "not ");
920 printf ("ISA Bus is %sreseted\n",
921 ((scsirst
& 0x40) == 0x40) ? "" : "not ");
922 printf ("Super IO is %sreseted\n",
923 ((scsirst
& 0x80) == 0x80) ? "" : "not ");
926 void user_led0 (unsigned char on
)
929 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x1));
931 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfe));
934 void user_led1 (unsigned char on
)
937 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) | 0x2));
939 out8 (PLD_LED_USER_REG
, (in8 (PLD_LED_USER_REG
) & 0xfd));
942 void ide_set_reset (int idereset
)
944 /* if reset = 1 IDE reset will be asserted */
945 unsigned char resreg
;
947 resreg
= in8 (PLD_SCSI_RST_REG
);
954 out8 (PLD_SCSI_RST_REG
, resreg
);