board/ms7722se/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2007
   3  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   4  *
   5  * Copyright (C) 2007
   6  * Kenati Technologies, Inc.
   7  *
   8  * board/ms7722se/lowlevel_init.S
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <version.h>
  28
  29 #include <asm/processor.h>
  30
  31 /*
  32  * Board specific low level init code, called _very_ early in the
  33  * startup sequence. Relocation to SDRAM has not happened yet, no
  34  * stack is available, bss section has not been initialised, etc.
  35  *
  36  * (Note: As no stack is available, no subroutines can be called...).
  37  */
  38
  39         .global lowlevel_init
  40
  41         .text
  42         .align  2
  43
  44 lowlevel_init:
  45
  46         /* Address of Cache Control Register */
  47         mov.l   CCR_A, r1
  48         /*Instruction Cache Invalidate */
  49         mov.l   CCR_D, r0
  50         mov.l   r0, @r1
  51
  52         /* Address of MMU Control Register */
  53         mov.l   MMUCR_A, r1
  54         /* TI == TLB Invalidate bit */
  55         mov.l   MMUCR_D, r0
  56         mov.l   r0, @r1
  57
  58         /* Address of Power Control Register 0 */
  59         mov.l   MSTPCR0_A, r1
  60         mov.l   MSTPCR0_D, r0
  61         mov.l   r0, @r1
  62
  63         /* Address of Power Control Register 2 */
  64         mov.l   MSTPCR2_A, r1
  65         mov.l   MSTPCR2_D, r0
  66         mov.l   r0, @r1
  67
  68         mov.l   SBSCR_A, r1
  69         mov.w   SBSCR_D, r0
  70         mov.w   r0, @r1
  71
  72         mov.l   PSCR_A, r1
  73         mov.w   PSCR_D, r0
  74         mov.w   r0, @r1
  75
  76         /* 0xA4520004 (Watchdog Control / Status Register) */
  77 !       mov.l   RWTCSR_A, r1
  78         /* 0xA507 -> timer_STOP/WDT_CLK=max */
  79 !       mov.w   RWTCSR_D_1, r0
  80 !       mov.w   r0, @r1
  81
  82         /* 0xA4520000 (Watchdog Count Register) */
  83         mov.l   RWTCNT_A, r1
  84         /*0x5A00 -> Clear */
  85         mov.w   RWTCNT_D, r0
  86         mov.w   r0, @r1
  87
  88         /* 0xA4520004 (Watchdog Control / Status Register) */
  89         mov.l   RWTCSR_A, r1
  90         /* 0xA504 -> timer_STOP/CLK=500ms */
  91         mov.w   RWTCSR_D_2, r0
  92         mov.w   r0, @r1
  93
  94         /* 0xA4150000 Frequency control register */
  95         mov.l   FRQCR_A, r1
  96         mov.l   FRQCR_D, r0     !
  97         mov.l   r0, @r1
  98
  99         mov.l   CCR_A, r1
 100         mov.l   CCR_D_2, r0
 101         mov.l   r0, @r1
 102
 103 bsc_init:
 104
 105         mov.l   PSELA_A, r1
 106         mov.w   PSELA_D, r0
 107         mov.w   r0, @r1
 108
 109         mov.l   DRVCR_A, r1
 110         mov.w   DRVCR_D, r0
 111         mov.w   r0, @r1
 112
 113         mov.l   PCCR_A, r1
 114         mov.w   PCCR_D, r0
 115         mov.w   r0, @r1
 116
 117         mov.l   PECR_A, r1
 118         mov.w   PECR_D, r0
 119         mov.w   r0, @r1
 120
 121         mov.l   PJCR_A, r1
 122         mov.w   PJCR_D, r0
 123         mov.w   r0, @r1
 124
 125         mov.l   PXCR_A, r1
 126         mov.w   PXCR_D, r0
 127         mov.w   r0, @r1
 128
 129         mov.l   CMNCR_A, r1     ! CMNCR address -> R1
 130         mov.l   CMNCR_D, r0     ! CMNCR data    -> R0
 131         mov.l   r0, @r1         ! CMNCR set
 132
 133         mov.l   CS0BCR_A, r1    ! CS0BCR address -> R1
 134         mov.l   CS0BCR_D, r0    ! CS0BCR data    -> R0
 135         mov.l   r0, @r1         ! CS0BCR set
 136
 137         mov.l   CS2BCR_A, r1    ! CS2BCR address -> R1
 138         mov.l   CS2BCR_D, r0    ! CS2BCR data    -> R0
 139         mov.l   r0, @r1         ! CS2BCR set
 140
 141         mov.l   CS4BCR_A, r1    ! CS4BCR address -> R1
 142         mov.l   CS4BCR_D, r0    ! CS4BCR data    -> R0
 143         mov.l   r0, @r1         ! CS4BCR set
 144
 145         mov.l   CS5ABCR_A, r1   ! CS5ABCR address -> R1
 146         mov.l   CS5ABCR_D, r0   ! CS5ABCR data    -> R0
 147         mov.l   r0, @r1         ! CS5ABCR set
 148
 149         mov.l   CS5BBCR_A, r1   ! CS5BBCR address -> R1
 150         mov.l   CS5BBCR_D, r0   ! CS5BBCR data    -> R0
 151         mov.l   r0, @r1         ! CS5BBCR set
 152
 153         mov.l   CS6ABCR_A, r1   ! CS6ABCR address -> R1
 154         mov.l   CS6ABCR_D, r0   ! CS6ABCR data    -> R0
 155         mov.l   r0, @r1         ! CS6ABCR set
 156
 157         mov.l   CS0WCR_A, r1    ! CS0WCR address -> R1
 158         mov.l   CS0WCR_D, r0    ! CS0WCR data    -> R0
 159         mov.l   r0, @r1         ! CS0WCR set
 160
 161         mov.l   CS2WCR_A, r1    ! CS2WCR address -> R1
 162         mov.l   CS2WCR_D, r0    ! CS2WCR data    -> R0
 163         mov.l   r0, @r1         ! CS2WCR set
 164
 165         mov.l   CS4WCR_A, r1    ! CS4WCR address -> R1
 166         mov.l   CS4WCR_D, r0    ! CS4WCR data    -> R0
 167         mov.l   r0, @r1         ! CS4WCR set
 168
 169         mov.l   CS5AWCR_A, r1   ! CS5AWCR address -> R1
 170         mov.l   CS5AWCR_D, r0   ! CS5AWCR data    -> R0
 171         mov.l   r0, @r1         ! CS5AWCR set
 172
 173         mov.l   CS5BWCR_A, r1   ! CS5BWCR address -> R1
 174         mov.l   CS5BWCR_D, r0   ! CS5BWCR data    -> R0
 175         mov.l   r0, @r1         ! CS5BWCR set
 176
 177         mov.l   CS6AWCR_A, r1   ! CS6AWCR address -> R1
 178         mov.l   CS6AWCR_D, r0   ! CS6AWCR data    -> R0
 179         mov.l   r0, @r1         ! CS6AWCR set
 180
 181         ! SDRAM initialization
 182         mov.l   SDCR_A, r1      ! SB_SDCR address -> R1
 183         mov.l   SDCR_D, r0      ! SB_SDCR data    -> R0
 184         mov.l   r0, @r1         ! SB_SDCR set
 185
 186         mov.l   SDWCR_A, r1     ! SB_SDWCR address -> R1
 187         mov.l   SDWCR_D, r0     ! SB_SDWCR data    -> R0
 188         mov.l   r0, @r1         ! SB_SDWCR set
 189
 190         mov.l   SDPCR_A, r1     ! SB_SDPCR address -> R1
 191         mov.l   SDPCR_D, r0     ! SB_SDPCR data    -> R0
 192         mov.l   r0, @r1         ! SB_SDPCR set
 193
 194         mov.l   RTCOR_A, r1     ! SB_RTCOR address -> R1
 195         mov.l   RTCOR_D, r0     ! SB_RTCOR data    -> R0
 196         mov.l   r0, @r1         ! SB_RTCOR set
 197
 198         mov.l   RTCSR_A, r1     ! SB_RTCSR address -> R1
 199         mov.l   RTCSR_D, r0     ! SB_RTCSR data    -> R0
 200         mov.l   r0, @r1         ! SB_RTCSR set
 201
 202         mov.l   SDMR3_A, r1     ! SDMR3 address -> R1
 203         mov     #0x00, r0       ! SDMR3 data    -> R0
 204         mov.b   r0, @r1         ! SDMR3 set
 205
 206         ! BL bit off (init = ON) (?!?)
 207
 208         stc     sr, r0                          ! BL bit off(init=ON)
 209         mov.l   SR_MASK_D, r1
 210         and     r1, r0
 211         ldc     r0, sr
 212
 213         rts
 214         mov     #0, r0
 215
 216         .align  2
 217
 218 CCR_A:          .long   CCR
 219 MMUCR_A:        .long   MMUCR
 220 MSTPCR0_A:      .long   MSTPCR0
 221 MSTPCR2_A:      .long   MSTPCR2
 222 SBSCR_A:        .long   SBSCR
 223 PSCR_A:         .long   PSCR
 224 RWTCSR_A:       .long   RWTCSR
 225 RWTCNT_A:       .long   RWTCNT
 226 FRQCR_A:        .long   FRQCR
 227
 228 CCR_D:          .long   0x00000800
 229 CCR_D_2:        .long   0x00000103
 230 MMUCR_D:        .long   0x00000004
 231 MSTPCR0_D:      .long   0x00001001
 232 MSTPCR2_D:      .long   0xffffffff
 233 FRQCR_D:        .long   0x07022538
 234
 235 PSELA_A:        .long   0xa405014E
 236 PSELA_D:        .word   0x0A10
 237         .align 2
 238
 239 DRVCR_A:        .long   0xa405018A
 240 DRVCR_D:        .word   0x0554
 241         .align 2
 242
 243 PCCR_A:         .long   0xa4050104
 244 PCCR_D:         .word   0x8800
 245         .align 2
 246
 247 PECR_A:         .long   0xa4050108
 248 PECR_D:         .word   0x0000
 249         .align 2
 250
 251 PJCR_A:         .long   0xa4050110
 252 PJCR_D:         .word   0x1000
 253         .align 2
 254
 255 PXCR_A:         .long   0xa4050148
 256 PXCR_D:         .word   0x0AAA
 257         .align 2
 258
 259 CMNCR_A:        .long   CMNCR
 260 CMNCR_D:        .long   0x00000013
 261 CS0BCR_A:       .long   CS0BCR          ! Flash bank 1
 262 CS0BCR_D:       .long   0x24920400
 263 CS2BCR_A:       .long   CS2BCR          ! SRAM
 264 CS2BCR_D:       .long   0x24920400
 265 CS4BCR_A:       .long   CS4BCR          ! FPGA, PCMCIA, USB, ext slot
 266 CS4BCR_D:       .long   0x24920400
 267 CS5ABCR_A:      .long   CS5ABCR         ! Ext slot
 268 CS5ABCR_D:      .long   0x24920400
 269 CS5BBCR_A:      .long   CS5BBCR         ! USB controller
 270 CS5BBCR_D:      .long   0x24920400
 271 CS6ABCR_A:      .long   CS6ABCR         ! Ethernet
 272 CS6ABCR_D:      .long   0x24920400
 273
 274 CS0WCR_A:       .long   CS0WCR
 275 CS0WCR_D:       .long   0x00000300
 276 CS2WCR_A:       .long   CS2WCR
 277 CS2WCR_D:       .long   0x00000300
 278 CS4WCR_A:       .long   CS4WCR
 279 CS4WCR_D:       .long   0x00000300
 280 CS5AWCR_A:      .long   CS5AWCR
 281 CS5AWCR_D:      .long   0x00000300
 282 CS5BWCR_A:      .long   CS5BWCR
 283 CS5BWCR_D:      .long   0x00000300
 284 CS6AWCR_A:      .long   CS6AWCR
 285 CS6AWCR_D:      .long   0x00000300
 286
 287 SDCR_A:         .long   SBSC_SDCR
 288 SDCR_D:         .long   0x00020809
 289 SDWCR_A:        .long   SBSC_SDWCR
 290 SDWCR_D:        .long   0x00164d0d
 291 SDPCR_A:        .long   SBSC_SDPCR
 292 SDPCR_D:        .long   0x00000087
 293 RTCOR_A:        .long   SBSC_RTCOR
 294 RTCOR_D:        .long   0xA55A0034
 295 RTCSR_A:        .long   SBSC_RTCSR
 296 RTCSR_D:        .long   0xA55A0010
 297 SDMR3_A:        .long   0xFE500180
 298
 299         .align  1
 300
 301 SBSCR_D:        .word   0x0040
 302 PSCR_D:         .word   0x0000
 303 RWTCSR_D_1:     .word   0xA507
 304 RWTCSR_D_2:     .word   0xA507
 305 RWTCNT_D:       .word   0x5A00
 306         .align  2
 307
 308 SR_MASK_D:      .long   0xEFFFFF0F