board/mvs1/mvs1.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Changes for MATRIX Vision MVsensor (C) Copyright 2001
   6  * MATRIX Vision GmbH / hg, info@matrix-vision.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc8xx.h>
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 static long int dram_size (long int, long int *, long int);
  33
  34 /* ------------------------------------------------------------------------- */
  35
  36 #define _NOT_USED_      0xFFFFFFFF
  37
  38 const uint sdram_table[] =
  39 {
  40         /*
  41          * Single Read. (Offset 0 in UPMA RAM)
  42          */
  43         0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  44         0x1FF5FC47, /* last */
  45         /*
  46          * SDRAM Initialization (offset 5 in UPMA RAM)
  47          *
  48          * This is no UPM entry point. The following definition uses
  49          * the remaining space to establish an initialization
  50          * sequence, which is executed by a RUN command.
  51          *
  52          */
  53                     0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  54         /*
  55          * Burst Read. (Offset 8 in UPMA RAM)
  56          */
  57         0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  58         0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  59         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  60         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  61         /*
  62          * Single Write. (Offset 18 in UPMA RAM)
  63          */
  64         0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
  65         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66         /*
  67          * Burst Write. (Offset 20 in UPMA RAM)
  68          */
  69         0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  70         0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
  71                                             _NOT_USED_,
  72         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74         /*
  75          * Refresh  (Offset 30 in UPMA RAM)
  76          */
  77         0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  78         0xFFFFFC84, 0xFFFFFC07, /* last */
  79                                 _NOT_USED_, _NOT_USED_,
  80         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  81         /*
  82          * Exception. (Offset 3c in UPMA RAM)
  83          */
  84         0x7FFFFC07, /* last */
  85                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  86 };
  87
  88 /* ------------------------------------------------------------------------- */
  89
  90
  91 /*
  92  * Check Board Identity:
  93  */
  94
  95 int checkboard (void)
  96 {
  97         puts ("Board: MATRIX Vision MVsensor\n");
  98         return 0;
  99 }
 100
 101
 102
 103 #ifdef DO_RAM_TEST
 104 /* ------------------------------------------------------------------------- */
 105
 106 /*
 107  * Test SDRAM by writing its address to itself and reading several times
 108 */
 109 #define READ_RUNS 4
 110 static void test_dram (unsigned long *start, unsigned long *end)
 111 {
 112         unsigned long *addr;
 113         unsigned long value;
 114         int read_runs, errors, addr_errors;
 115
 116         printf ("\nChecking SDRAM from %p to %p\n", start, end);
 117         udelay (1000000);
 118         for (addr = start; addr < end; addr++)
 119                 *addr = (unsigned long) addr;
 120
 121         for (addr = start, addr_errors = 0; addr < end; addr++) {
 122                 for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) {
 123                         if ((value = *addr) != (unsigned long) addr)
 124                                 errors++;
 125                 }
 126                 if (errors > 0) {
 127                         addr_errors++;
 128                         printf ("SDRAM errors (%d) at %p, last read  = %ld\n",
 129                                         errors, addr, value);
 130                         udelay (10000);
 131                 }
 132         }
 133         printf ("SDRAM check finished, total errors = %d\n", addr_errors);
 134 }
 135 #endif                                                  /*  DO_RAM_TEST */
 136
 137
 138 /* ------------------------------------------------------------------------- */
 139
 140 long int initdram (int board_type)
 141 {
 142         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 143         volatile memctl8xx_t *memctl = &immap->im_memctl;
 144         long int size_b0, size_b1, size8, size9;
 145
 146         upmconfig (UPMA, (uint *) sdram_table,
 147                            sizeof (sdram_table) / sizeof (uint));
 148
 149         /*
 150          * Preliminary prescaler for refresh (depends on number of
 151          * banks): This value is selected for four cycles every 62.4 us
 152          * with two SDRAM banks or four cycles every 31.2 us with one
 153          * bank. It will be adjusted after memory sizing.
 154          */
 155         memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 156
 157         memctl->memc_mar = 0x00000088;
 158
 159         /*
 160          * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 161          * preliminary addresses - these have to be modified after the
 162          * SDRAM size has been determined.
 163          */
 164         memctl->memc_or2 = CFG_OR2_PRELIM;
 165         memctl->memc_br2 = CFG_BR2_PRELIM;
 166
 167 #if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM)
 168         if (board_type == 0) {          /* "L" type boards have only one bank SDRAM */
 169                 memctl->memc_or3 = CFG_OR3_PRELIM;
 170                 memctl->memc_br3 = CFG_BR3_PRELIM;
 171         }
 172 #endif
 173
 174         memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
 175
 176         udelay (200);
 177
 178         /* perform SDRAM initializsation sequence */
 179
 180         memctl->memc_mcr = 0x80004105;  /* SDRAM bank 0 */
 181         udelay (1);
 182         memctl->memc_mcr = 0x80004230;  /* SDRAM bank 0 - execute twice */
 183         udelay (1);
 184
 185         if (board_type == 0) {          /* "L" type boards have only one bank SDRAM */
 186                 memctl->memc_mcr = 0x80006105;  /* SDRAM bank 1 */
 187                 udelay (1);
 188                 memctl->memc_mcr = 0x80006230;  /* SDRAM bank 1 - execute twice */
 189                 udelay (1);
 190         }
 191
 192         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 193
 194         udelay (1000);
 195
 196         /*
 197          * Check Bank 0 Memory Size for re-configuration
 198          *
 199          * try 8 column mode
 200          */
 201         size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
 202                                            SDRAM_MAX_SIZE);
 203
 204         udelay (1000);
 205         /*
 206          * try 9 column mode
 207          */
 208         size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
 209                                            SDRAM_MAX_SIZE);
 210
 211         if (size8 < size9) {            /* leave configuration at 9 columns */
 212                 size_b0 = size9;
 213         } else {                                        /* back to 8 columns            */
 214                 size_b0 = size8;
 215                 memctl->memc_mamr = CFG_MAMR_8COL;
 216                 udelay (500);
 217         }
 218
 219         if (board_type == 0) {          /* "L" type boards have only one bank SDRAM */
 220                 /*
 221                  * Check Bank 1 Memory Size
 222                  * use current column settings
 223                  * [9 column SDRAM may also be used in 8 column mode,
 224                  *  but then only half the real size will be used.]
 225                  */
 226 #if defined (SDRAM_BASE3_PRELIM)
 227                 size_b1 =
 228                                 dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
 229                                                    SDRAM_MAX_SIZE);
 230 #else
 231                 size_b1 = 0;
 232 #endif
 233         } else {
 234                 size_b1 = 0;
 235         }
 236
 237         udelay (1000);
 238
 239         /*
 240          * Adjust refresh rate depending on SDRAM type, both banks
 241          * For types > 128 MBit leave it at the current (fast) rate
 242          */
 243         if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 244                 /* reduce to 15.6 us (62.4 us / quad) */
 245                 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 246                 udelay (1000);
 247         }
 248
 249         /*
 250          * Final mapping: map bigger bank first
 251          */
 252         if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 253
 254                 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 255                 memctl->memc_br3 =
 256                                 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 257
 258                 if (size_b0 > 0) {
 259                         /*
 260                          * Position Bank 0 immediately above Bank 1
 261                          */
 262                         memctl->memc_or2 =
 263                                         ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 264                         memctl->memc_br2 =
 265                                         ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 266                                         + size_b1;
 267                 } else {
 268                         unsigned long reg;
 269
 270                         /*
 271                          * No bank 0
 272                          *
 273                          * invalidate bank
 274                          */
 275                         memctl->memc_br2 = 0;
 276
 277                         /* adjust refresh rate depending on SDRAM type, one bank */
 278                         reg = memctl->memc_mptpr;
 279                         reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
 280                         memctl->memc_mptpr = reg;
 281                 }
 282
 283         } else {                                        /* SDRAM Bank 0 is bigger - map first   */
 284
 285                 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 286                 memctl->memc_br2 =
 287                                 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 288
 289                 if (size_b1 > 0) {
 290                         /*
 291                          * Position Bank 1 immediately above Bank 0
 292                          */
 293                         memctl->memc_or3 =
 294                                         ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 295                         memctl->memc_br3 =
 296                                         ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 297                                         + size_b0;
 298                 } else {
 299                         unsigned long reg;
 300
 301                         /*
 302                          * No bank 1
 303                          *
 304                          * invalidate bank
 305                          */
 306                         memctl->memc_br3 = 0;
 307
 308                         /* adjust refresh rate depending on SDRAM type, one bank */
 309                         reg = memctl->memc_mptpr;
 310                         reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
 311                         memctl->memc_mptpr = reg;
 312                 }
 313         }
 314
 315         udelay (10000);
 316
 317 #ifdef DO_RAM_TEST
 318         if (size_b0 > 0)
 319                 test_dram ((unsigned long *) CFG_SDRAM_BASE,
 320                                    (unsigned long *) (CFG_SDRAM_BASE + size_b0));
 321 #endif
 322
 323         return (size_b0 + size_b1);
 324 }
 325
 326 /* ------------------------------------------------------------------------- */
 327
 328 /*
 329  * Check memory range for valid RAM. A simple memory test determines
 330  * the actually available RAM size between addresses `base' and
 331  * `base + maxsize'. Some (not all) hardware errors are detected:
 332  * - short between address lines
 333  * - short between data lines
 334  */
 335
 336 static long int dram_size (long int mamr_value, long int *base,
 337                                                    long int maxsize)
 338 {
 339         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 340         volatile memctl8xx_t *memctl = &immap->im_memctl;
 341         volatile long int *addr;
 342         long int cnt, val;
 343
 344
 345         memctl->memc_mamr = mamr_value;
 346
 347         for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
 348                 addr = base + cnt;              /* pointer arith! */
 349
 350                 *addr = ~cnt;
 351         }
 352
 353         /* write 0 to base address */
 354         addr = base;
 355         *addr = 0;
 356
 357         /* check at base address */
 358         if ((val = *addr) != 0) {
 359                 return (0);
 360         }
 361
 362         for (cnt = 1;; cnt <<= 1) {
 363                 addr = base + cnt;              /* pointer arith! */
 364
 365                 val = *addr;
 366
 367                 if (val != (~cnt)) {
 368                         return (cnt * sizeof (long));
 369                 }
 370         }
 371         /* NOTREACHED */
 372 }
 373
 374
 375 /* ------------------------------------------------------------------------- */
 376
 377 u8 *dhcp_vendorex_prep (u8 * e)
 378 {
 379         char *ptr;
 380
 381 /* DHCP vendor-class-identifier = 60 */
 382         if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
 383                 *e++ = 60;
 384                 *e++ = strlen (ptr);
 385                 while (*ptr)
 386                         *e++ = *ptr++;
 387         }
 388 /* my DHCP_CLIENT_IDENTIFIER = 61 */
 389         if ((ptr = getenv ("dhcp_client_id"))) {
 390                 *e++ = 61;
 391                 *e++ = strlen (ptr);
 392                 while (*ptr)
 393                         *e++ = *ptr++;
 394         }
 395
 396         return e;
 397 }
 398
 399
 400 /* ------------------------------------------------------------------------- */
 401 u8 *dhcp_vendorex_proc (u8 * popt)
 402 {
 403         return NULL;
 404 }