board/nc650/nc650.c

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <config.h>
  26 #include <mpc8xx.h>
  27
  28 /*
  29  *  Memory Controller Using
  30  *
  31  *  CS0 - Flash memory            (0x40000000)
  32  *  CS3 - SDRAM                   (0x00000000}
  33  */
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 #define _not_used_      0xffffffff
  38
  39 const uint sdram_table[] = {
  40         /* single read. (offset 0 in upm RAM) */
  41         0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
  42         0x1ff77c47,
  43
  44         /* MRS initialization (offset 5) */
  45
  46         0x1ff77c34, 0xefeabc34, 0x1fb57c35,
  47
  48         /* burst read. (offset 8 in upm RAM) */
  49         0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
  50         0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
  51         _not_used_, _not_used_, _not_used_, _not_used_,
  52         _not_used_, _not_used_, _not_used_, _not_used_,
  53
  54         /* single write. (offset 18 in upm RAM) */
  55         0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
  56         _not_used_, _not_used_, _not_used_, _not_used_,
  57
  58         /* burst write. (offset 20 in upm RAM) */
  59         0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  60         0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
  61         _not_used_, _not_used_, _not_used_, _not_used_,
  62         _not_used_, _not_used_, _not_used_, _not_used_,
  63
  64         /* refresh. (offset 30 in upm RAM) */
  65         0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  66         0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
  67         _not_used_, _not_used_, _not_used_, _not_used_,
  68
  69         /* exception. (offset 3c in upm RAM) */
  70         0x7ffffc07, _not_used_, _not_used_, _not_used_
  71 };
  72
  73 /* ------------------------------------------------------------------------- */
  74
  75 /*
  76  * Check Board Identity:
  77  */
  78
  79 int checkboard (void)
  80 {
  81         puts ("Board: NC650\n");
  82         return 0;
  83 }
  84
  85 /* ------------------------------------------------------------------------- */
  86
  87 static long int dram_size (long int, long int *, long int);
  88
  89 /* ------------------------------------------------------------------------- */
  90
  91 long int initdram (int board_type)
  92 {
  93         volatile immap_t *immap = (immap_t *) CFG_IMMR;
  94         volatile memctl8xx_t *memctl = &immap->im_memctl;
  95         long int size8, size9;
  96         long int size_b0 = 0;
  97         unsigned long reg;
  98
  99         upmconfig (UPMA, (uint *) sdram_table,
 100                            sizeof (sdram_table) / sizeof (uint));
 101
 102         /*
 103          * Preliminary prescaler for refresh (depends on number of
 104          * banks): This value is selected for four cycles every 62.4 us
 105          * with two SDRAM banks or four cycles every 31.2 us with one
 106          * bank. It will be adjusted after memory sizing.
 107          */
 108         memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
 109
 110         memctl->memc_mar = 0x00000088;
 111
 112         /*
 113          * Map controller bank 1 to the SDRAM bank at
 114          * preliminary address - these have to be modified after the
 115          * SDRAM size has been determined.
 116          */
 117         memctl->memc_or3 = CFG_OR3_PRELIM;
 118         memctl->memc_br3 = CFG_BR3_PRELIM;
 119
 120         memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
 121
 122         udelay (200);
 123
 124         /* perform SDRAM initializsation sequence */
 125
 126         memctl->memc_mcr = 0x80006105;  /* SDRAM bank 0 */
 127         udelay (200);
 128         memctl->memc_mcr = 0x80006230;  /* SDRAM bank 0 - execute twice */
 129         udelay (200);
 130
 131         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 132
 133         udelay (1000);
 134
 135         /*
 136          * Check Bank 0 Memory Size for re-configuration
 137          *
 138          * try 8 column mode
 139          */
 140         size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
 141                                            SDRAM_MAX_SIZE);
 142
 143         udelay (1000);
 144
 145         /*
 146          * try 9 column mode
 147          */
 148         size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
 149                                           SDRAM_MAX_SIZE);
 150
 151         udelay (1000);
 152
 153         if (size8 < size9) {
 154                 size_b0 = size9;
 155         } else {
 156                 size_b0 = size8;
 157                 memctl->memc_mamr = CFG_MAMR_8COL;
 158                 udelay (500);
 159         }
 160
 161         /*
 162          * Adjust refresh rate depending on SDRAM type, both banks.
 163          * For types > 128 MBit leave it at the current (fast) rate
 164          */
 165         if ((size_b0 < 0x02000000)) {
 166                 /* reduce to 15.6 us (62.4 us / quad) */
 167                 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
 168                 udelay (1000);
 169         }
 170
 171         /*
 172          * Final mapping
 173          */
 174
 175         memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
 176         memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 177
 178         /* adjust refresh rate depending on SDRAM type, one bank */
 179         reg = memctl->memc_mptpr;
 180         reg >>= 1;                                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
 181         memctl->memc_mptpr = reg;
 182
 183         udelay (10000);
 184
 185         return (size_b0);
 186 }
 187
 188 /* ------------------------------------------------------------------------- */
 189
 190 /*
 191  * Check memory range for valid RAM. A simple memory test determines
 192  * the actually available RAM size between addresses `base' and
 193  * `base + maxsize'. Some (not all) hardware errors are detected:
 194  * - short between address lines
 195  * - short between data lines
 196  */
 197
 198 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 199 {
 200         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 201         volatile memctl8xx_t *memctl = &immap->im_memctl;
 202
 203         memctl->memc_mamr = mamr_value;
 204
 205         return (get_ram_size(base, maxsize));
 206 }
 207
 208 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 209 void nand_init(void)
 210 {
 211         extern unsigned long nand_probe(unsigned long physadr);
 212
 213         unsigned long totlen = nand_probe(CFG_NAND_BASE);
 214
 215         printf ("%4lu MB\n", totlen >> 20);
 216 }
 217 #endif