board/netstal/hcu5/sdram.c

   1 /*
   2  * (C) Copyright 2007
   3  * Niklaus Giger (Niklaus.Giger@netstal.com)
   4  * (C) Copyright 2006
   5  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   8  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   9  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  10  *
  11  * (C) Copyright 2006
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* define DEBUG for debug output */
  31 #undef DEBUG
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <asm/mmu.h>
  37 #include <ppc440.h>
  38
  39 void hcu_led_set(u32 value);
  40 void dcbz_area(u32 start_address, u32 num_bytes);
  41 void dflush(void);
  42
  43 #define DDR_DCR_BASE 0x10
  44 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
  45 #define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
  46
  47 #define DDR0_01_INT_MASK_MASK             0x000000FF
  48 #define DDR0_00_INT_ACK_ALL               0x7F000000
  49 #define DDR0_01_INT_MASK_ALL_ON           0x000000FF
  50 #define DDR0_01_INT_MASK_ALL_OFF          0x00000000
  51
  52 #define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
  53 #define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
  54 #define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
  55
  56 #define DDR0_22                         0x16
  57 /* ECC */
  58 #define DDR0_22_CTRL_RAW_MASK             0x03000000
  59 #define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not enabled */
  60 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC no correction */
  61 #define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* Not a ECC RAM*/
  62 #define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC correcting on */
  63 #define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
  64
  65 #ifdef CFG_ENABLE_SDRAM_CACHE
  66 #define MY_TLB_WORD2_I_ENABLE   0               /* enable caching on DDR2 */
  67 #else
  68 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
  69 #endif
  70
  71 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
  72
  73 #ifdef CONFIG_ADD_RAM_INFO
  74 void board_add_ram_info(int use_default)
  75 {
  76         PPC440_SYS_INFO board_cfg;
  77         u32 val;
  78         mfsdram(DDR0_22, val);
  79         val &= DDR0_22_CTRL_RAW_MASK;
  80         switch (val) {
  81         case DDR0_22_CTRL_RAW_ECC_DISABLE:
  82                 puts(" (ECC disabled");
  83                 break;
  84         case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
  85                 puts(" (ECC check only");
  86                 break;
  87         case DDR0_22_CTRL_RAW_NO_ECC_RAM:
  88                 puts(" (no ECC ram");
  89                 break;
  90         case DDR0_22_CTRL_RAW_ECC_ENABLE:
  91                 puts(" (ECC enabled");
  92                 break;
  93         }
  94
  95         get_sys_info(&board_cfg);
  96         printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  97
  98         mfsdram(DDR0_03, val);
  99         val = DDR0_03_CASLAT_DECODE(val);
 100         printf(", CL%d)", val);
 101 }
 102 #endif
 103
 104 /*--------------------------------------------------------------------
 105  * wait_for_dlllock.
 106  *--------------------------------------------------------------------*/
 107 static int wait_for_dlllock(void)
 108 {
 109         unsigned long val;
 110         int wait = 0;
 111
 112         /* -----------------------------------------------------------+
 113          * Wait for the DCC master delay line to finish calibration
 114          * ----------------------------------------------------------*/
 115         mtdcr(ddrcfga, DDR0_17);
 116         val = DDR0_17_DLLLOCKREG_UNLOCKED;
 117
 118         while (wait != 0xffff) {
 119                 val = mfdcr(ddrcfgd);
 120                 if ((val & DDR0_17_DLLLOCKREG_MASK) ==
 121                     DDR0_17_DLLLOCKREG_LOCKED)
 122                         /* dlllockreg bit on */
 123                         return 0;
 124                 else
 125                         wait++;
 126         }
 127         debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
 128         debug("Waiting for dlllockreg bit to raise\n");
 129
 130         return -1;
 131 }
 132
 133 /***********************************************************************
 134  *
 135  * sdram_panic -- Panic if we cannot configure the sdram correctly
 136  *
 137  ************************************************************************/
 138 void sdram_panic(const char *reason)
 139 {
 140         printf("\n%s: reason %s",  __FUNCTION__,  reason);
 141         hcu_led_set(0xff);
 142         while (1) {
 143         }
 144         /* Never return */
 145 }
 146
 147 #ifdef CONFIG_DDR_ECC
 148 static void blank_string(int size)
 149 {
 150         int i;
 151
 152         for (i=0; i<size; i++)
 153                 putc('\b');
 154         for (i=0; i<size; i++)
 155                 putc(' ');
 156         for (i=0; i<size; i++)
 157                 putc('\b');
 158 }
 159 /*---------------------------------------------------------------------------+
 160  * program_ecc.
 161  *---------------------------------------------------------------------------*/
 162 static void program_ecc(unsigned long start_address, unsigned long num_bytes,
 163                         unsigned long tlb_word2_i_value)
 164 {
 165         unsigned long current_address= start_address;
 166         int loopi = 0;
 167         u32 val;
 168
 169         char str[] = "ECC generation -";
 170         char slash[] = "\\|/-\\|/-";
 171
 172         sync();
 173         eieio();
 174
 175         puts(str);
 176
 177         if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
 178                 /* ECC bit set method for non-cached memory */
 179                 /* This takes various seconds */
 180                 for(current_address = 0; current_address < num_bytes;
 181                      current_address += sizeof(u32)) {
 182                         *(u32 *)current_address = 0;
 183                         if ((current_address % (2 << 20)) == 0) {
 184                                 putc('\b');
 185                                 putc(slash[loopi++ % 8]);
 186                         }
 187                 }
 188         } else {
 189                 /* ECC bit set method for cached memory */
 190                 /* Fast method, no noticeable delay */
 191                 dcbz_area(start_address, num_bytes);
 192                 dflush();
 193         }
 194         blank_string(strlen(str));
 195
 196         /* Clear error status */
 197         mfsdram(DDR0_00, val);
 198         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 199
 200         /*
 201          * Clear possible errors
 202          * If not done, then we could get an interrupt later on when
 203          * exceptions are enabled.
 204          */
 205         mtspr(mcsr, mfspr(mcsr));
 206
 207         /* Set 'int_mask' parameter to functionnal value */
 208         mfsdram(DDR0_01, val);
 209         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
 210                           DDR0_01_INT_MASK_ALL_OFF));
 211
 212         return;
 213 }
 214
 215 #endif
 216
 217 /***********************************************************************
 218  *
 219  * initdram -- 440EPx's DDR controller is a DENALI Core
 220  *
 221  ************************************************************************/
 222 long int initdram (int board_type)
 223 {
 224 #define HCU_HW_SDRAM_CONFIG_MASK 0x7
 225 #define INVALID_HW_CONFIG   "Invalid HW-Config"
 226         u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
 227         unsigned int dram_size = 0;
 228
 229         mtsdram(DDR0_02, 0x00000000);
 230
 231         /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
 232         mtsdram(DDR0_00, 0x0000190A);
 233         mtsdram(DDR0_01, 0x01000000);
 234         mtsdram(DDR0_03, 0x02030602);
 235         mtsdram(DDR0_04, 0x0A020200);
 236         mtsdram(DDR0_05, 0x02020307);
 237         switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
 238         case 0:
 239                 dram_size = 128 * 1024 * 1024 ;
 240                 mtsdram(DDR0_06, 0x0102C80D);  /* 128MB RAM */
 241                 mtsdram(DDR0_11, 0x000FC800);  /* 128MB RAM */
 242                 mtsdram(DDR0_43, 0x030A0300);  /* 128MB RAM */
 243                 break;
 244         case 1:
 245                 dram_size = 256 * 1024 * 1024 ;
 246                 mtsdram(DDR0_06, 0x0102C812);  /* 256MB RAM */
 247                 mtsdram(DDR0_11, 0x0014C800);  /* 256MB RAM */
 248                 mtsdram(DDR0_43, 0x030A0200);  /* 256MB RAM */
 249                 break;
 250         default:
 251                 sdram_panic(INVALID_HW_CONFIG);
 252                 break;
 253         }
 254         mtsdram(DDR0_07, 0x00090100);
 255         /*
 256          * TCPD=200 cycles of clock input is required to lock the DLL.
 257          * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
 258          */
 259         mtsdram(DDR0_08, 0x02C80001);
 260         mtsdram(DDR0_09, 0x00011D5F);
 261         mtsdram(DDR0_10, 0x00000100);
 262         mtsdram(DDR0_12, 0x00000003);
 263         mtsdram(DDR0_14, 0x00000000);
 264         mtsdram(DDR0_17, 0x1D000000);
 265         mtsdram(DDR0_18, 0x1D1D1D1D);
 266         mtsdram(DDR0_19, 0x1D1D1D1D);
 267         mtsdram(DDR0_20, 0x0B0B0B0B);
 268         mtsdram(DDR0_21, 0x0B0B0B0B);
 269         #define ECC_RAM  0x03267F0B
 270         #define NO_ECC_RAM  0x00267F0B
 271 #ifdef CONFIG_DDR_ECC
 272         mtsdram(DDR0_22, ECC_RAM);
 273 #else
 274         mtsdram(DDR0_22, NO_ECC_RAM);
 275 #endif
 276
 277         mtsdram(DDR0_23, 0x00000000);
 278         mtsdram(DDR0_24, 0x01020001);
 279         mtsdram(DDR0_26, 0x2D930517);
 280         mtsdram(DDR0_27, 0x00008236);
 281         mtsdram(DDR0_28, 0x00000000);
 282         mtsdram(DDR0_31, 0x00000000);
 283         mtsdram(DDR0_42, 0x01000006);
 284         mtsdram(DDR0_44, 0x00000003);
 285         mtsdram(DDR0_02, 0x00000001);
 286         wait_for_dlllock();
 287         mtsdram(DDR0_00, 0x40000000);  /* Zero init bit */
 288
 289         /*
 290          * Program tlb entries for this size (dynamic)
 291          */
 292         remove_tlb(CFG_SDRAM_BASE, 256 << 20);
 293         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 294
 295         /*
 296          * Setup 2nd TLB with same physical address but different virtual
 297          * address with cache enabled. This is done for fast ECC generation.
 298          */
 299         program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
 300
 301         /* Diminish RAM to initialize */
 302         dram_size = dram_size - 32 ;
 303 #ifdef CONFIG_DDR_ECC
 304         /*
 305          * If ECC is enabled, initialize the parity bits.
 306          */
 307         program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
 308 #endif
 309
 310         return (dram_size);
 311 }