board/netstal/hcu5/sdram.c

   1 /*
   2  * (C) Copyright 2007
   3  * Niklaus Giger (Niklaus.Giger@netstal.com)
   4  * (C) Copyright 2006
   5  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   8  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   9  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  10  *
  11  * (C) Copyright 2006
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* define DEBUG for debug output */
  31 #undef DEBUG
  32
  33 #include <common.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <asm/mmu.h>
  37 #include <ppc440.h>
  38
  39 void hcu_led_set(u32 value);
  40 void dcbz_area(u32 start_address, u32 num_bytes);
  41 void dflush(void);
  42
  43 #define DDR_DCR_BASE 0x10
  44 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
  45 #define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
  46
  47 #define DDR0_01_INT_MASK_MASK             0x000000FF
  48 #define DDR0_00_INT_ACK_ALL               0x7F000000
  49 #define DDR0_01_INT_MASK_ALL_ON           0x000000FF
  50 #define DDR0_01_INT_MASK_ALL_OFF          0x00000000
  51
  52 #define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
  53 #define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
  54 #define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
  55
  56 #define DDR0_22                         0x16
  57 /* ECC */
  58 #define DDR0_22_CTRL_RAW_MASK             0x03000000
  59 #define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not enabled */
  60 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC no correction */
  61 #define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* Not a ECC RAM*/
  62 #define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC correcting on */
  63 #define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
  64
  65 #ifdef CFG_ENABLE_SDRAM_CACHE
  66 #define MY_TLB_WORD2_I_ENABLE   0               /* enable caching on DDR2 */
  67 #else
  68 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
  69 #endif
  70
  71 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
  72
  73 void board_add_ram_info(int use_default)
  74 {
  75         PPC4xx_SYS_INFO board_cfg;
  76         u32 val;
  77         mfsdram(DDR0_22, val);
  78         val &= DDR0_22_CTRL_RAW_MASK;
  79         switch (val) {
  80         case DDR0_22_CTRL_RAW_ECC_DISABLE:
  81                 puts(" (ECC disabled");
  82                 break;
  83         case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
  84                 puts(" (ECC check only");
  85                 break;
  86         case DDR0_22_CTRL_RAW_NO_ECC_RAM:
  87                 puts(" (no ECC ram");
  88                 break;
  89         case DDR0_22_CTRL_RAW_ECC_ENABLE:
  90                 puts(" (ECC enabled");
  91                 break;
  92         }
  93
  94         get_sys_info(&board_cfg);
  95         printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
  96
  97         mfsdram(DDR0_03, val);
  98         val = DDR0_03_CASLAT_DECODE(val);
  99         printf(", CL%d)", val);
 100 }
 101
 102 /*--------------------------------------------------------------------
 103  * wait_for_dlllock.
 104  *--------------------------------------------------------------------*/
 105 static int wait_for_dlllock(void)
 106 {
 107         unsigned long val;
 108         int wait = 0;
 109
 110         /* -----------------------------------------------------------+
 111          * Wait for the DCC master delay line to finish calibration
 112          * ----------------------------------------------------------*/
 113         mtdcr(ddrcfga, DDR0_17);
 114         val = DDR0_17_DLLLOCKREG_UNLOCKED;
 115
 116         while (wait != 0xffff) {
 117                 val = mfdcr(ddrcfgd);
 118                 if ((val & DDR0_17_DLLLOCKREG_MASK) ==
 119                     DDR0_17_DLLLOCKREG_LOCKED)
 120                         /* dlllockreg bit on */
 121                         return 0;
 122                 else
 123                         wait++;
 124         }
 125         debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
 126         debug("Waiting for dlllockreg bit to raise\n");
 127
 128         return -1;
 129 }
 130
 131 /***********************************************************************
 132  *
 133  * sdram_panic -- Panic if we cannot configure the sdram correctly
 134  *
 135  ************************************************************************/
 136 void sdram_panic(const char *reason)
 137 {
 138         printf("\n%s: reason %s",  __FUNCTION__,  reason);
 139         hcu_led_set(0xff);
 140         while (1) {
 141         }
 142         /* Never return */
 143 }
 144
 145 #ifdef CONFIG_DDR_ECC
 146 static void blank_string(int size)
 147 {
 148         int i;
 149
 150         for (i=0; i<size; i++)
 151                 putc('\b');
 152         for (i=0; i<size; i++)
 153                 putc(' ');
 154         for (i=0; i<size; i++)
 155                 putc('\b');
 156 }
 157 /*---------------------------------------------------------------------------+
 158  * program_ecc.
 159  *---------------------------------------------------------------------------*/
 160 static void program_ecc(unsigned long start_address, unsigned long num_bytes,
 161                         unsigned long tlb_word2_i_value)
 162 {
 163         unsigned long current_address= start_address;
 164         int loopi = 0;
 165         u32 val;
 166
 167         char str[] = "ECC generation -";
 168         char slash[] = "\\|/-\\|/-";
 169
 170         sync();
 171         eieio();
 172
 173         puts(str);
 174
 175         if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
 176                 /* ECC bit set method for non-cached memory */
 177                 /* This takes various seconds */
 178                 for(current_address = 0; current_address < num_bytes;
 179                      current_address += sizeof(u32)) {
 180                         *(u32 *)current_address = 0;
 181                         if ((current_address % (2 << 20)) == 0) {
 182                                 putc('\b');
 183                                 putc(slash[loopi++ % 8]);
 184                         }
 185                 }
 186         } else {
 187                 /* ECC bit set method for cached memory */
 188                 /* Fast method, no noticeable delay */
 189                 dcbz_area(start_address, num_bytes);
 190                 dflush();
 191         }
 192         blank_string(strlen(str));
 193
 194         /* Clear error status */
 195         mfsdram(DDR0_00, val);
 196         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 197
 198         /*
 199          * Clear possible errors
 200          * If not done, then we could get an interrupt later on when
 201          * exceptions are enabled.
 202          */
 203         mtspr(mcsr, mfspr(mcsr));
 204
 205         /* Set 'int_mask' parameter to functionnal value */
 206         mfsdram(DDR0_01, val);
 207         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
 208                           DDR0_01_INT_MASK_ALL_OFF));
 209
 210         return;
 211 }
 212
 213 #endif
 214
 215 /***********************************************************************
 216  *
 217  * initdram -- 440EPx's DDR controller is a DENALI Core
 218  *
 219  ************************************************************************/
 220 long int initdram (int board_type)
 221 {
 222 #define HCU_HW_SDRAM_CONFIG_MASK 0x7
 223 #define INVALID_HW_CONFIG   "Invalid HW-Config"
 224         u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
 225         unsigned int dram_size = 0;
 226
 227         mtsdram(DDR0_02, 0x00000000);
 228
 229         /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
 230         mtsdram(DDR0_00, 0x0000190A);
 231         mtsdram(DDR0_01, 0x01000000);
 232         mtsdram(DDR0_03, 0x02030602);
 233         mtsdram(DDR0_04, 0x0A020200);
 234         mtsdram(DDR0_05, 0x02020307);
 235         switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
 236         case 0:
 237                 dram_size = 128 * 1024 * 1024 ;
 238                 mtsdram(DDR0_06, 0x0102C80D);  /* 128MB RAM */
 239                 mtsdram(DDR0_11, 0x000FC800);  /* 128MB RAM */
 240                 mtsdram(DDR0_43, 0x030A0300);  /* 128MB RAM */
 241                 break;
 242         case 1:
 243                 dram_size = 256 * 1024 * 1024 ;
 244                 mtsdram(DDR0_06, 0x0102C812);  /* 256MB RAM */
 245                 mtsdram(DDR0_11, 0x0014C800);  /* 256MB RAM */
 246                 mtsdram(DDR0_43, 0x030A0200);  /* 256MB RAM */
 247                 break;
 248         default:
 249                 sdram_panic(INVALID_HW_CONFIG);
 250                 break;
 251         }
 252         mtsdram(DDR0_07, 0x00090100);
 253         /*
 254          * TCPD=200 cycles of clock input is required to lock the DLL.
 255          * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
 256          */
 257         mtsdram(DDR0_08, 0x02C80001);
 258         mtsdram(DDR0_09, 0x00011D5F);
 259         mtsdram(DDR0_10, 0x00000100);
 260         mtsdram(DDR0_12, 0x00000003);
 261         mtsdram(DDR0_14, 0x00000000);
 262         mtsdram(DDR0_17, 0x1D000000);
 263         mtsdram(DDR0_18, 0x1D1D1D1D);
 264         mtsdram(DDR0_19, 0x1D1D1D1D);
 265         mtsdram(DDR0_20, 0x0B0B0B0B);
 266         mtsdram(DDR0_21, 0x0B0B0B0B);
 267         #define ECC_RAM  0x03267F0B
 268         #define NO_ECC_RAM  0x00267F0B
 269 #ifdef CONFIG_DDR_ECC
 270         mtsdram(DDR0_22, ECC_RAM);
 271 #else
 272         mtsdram(DDR0_22, NO_ECC_RAM);
 273 #endif
 274
 275         mtsdram(DDR0_23, 0x00000000);
 276         mtsdram(DDR0_24, 0x01020001);
 277         mtsdram(DDR0_26, 0x2D930517);
 278         mtsdram(DDR0_27, 0x00008236);
 279         mtsdram(DDR0_28, 0x00000000);
 280         mtsdram(DDR0_31, 0x00000000);
 281         mtsdram(DDR0_42, 0x01000006);
 282         mtsdram(DDR0_44, 0x00000003);
 283         mtsdram(DDR0_02, 0x00000001);
 284         wait_for_dlllock();
 285         mtsdram(DDR0_00, 0x40000000);  /* Zero init bit */
 286
 287         /*
 288          * Program tlb entries for this size (dynamic)
 289          */
 290         remove_tlb(CFG_SDRAM_BASE, 256 << 20);
 291         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 292
 293         /*
 294          * Setup 2nd TLB with same physical address but different virtual
 295          * address with cache enabled. This is done for fast ECC generation.
 296          */
 297         program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
 298
 299         /* Diminish RAM to initialize */
 300         dram_size = dram_size - 32 ;
 301 #ifdef CONFIG_DDR_ECC
 302         /*
 303          * If ECC is enabled, initialize the parity bits.
 304          */
 305         program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
 306 #endif
 307
 308         return (dram_size);
 309 }