board/netstar/setup.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
   5  * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <version.h>
  28
  29 _TEXT_BASE:
  30         .word   TEXT_BASE       /* SDRAM load addr from config.mk */
  31
  32 OMAP5910_LPG1_BASE:             .word 0xfffbd000
  33 OMAP5910_TIPB_SWITCHES_BASE:    .word 0xfffbc800
  34 OMAP5910_MPU_TC_BASE:           .word 0xfffecc00
  35 OMAP5910_MPU_CLKM_BASE:         .word 0xfffece00
  36 OMAP5910_ULPD_PWR_MNG_BASE:     .word 0xfffe0800
  37 OMAP5910_DPLL1_BASE:            .word 0xfffecf00
  38 OMAP5910_GPIO_BASE:             .word 0xfffce000
  39 OMAP5910_MPU_WD_TIMER_BASE:     .word 0xfffec800
  40 OMAP5910_MPUI_BASE:             .word 0xfffec900
  41
  42 _OMAP5910_ARM_CKCTL:            .word OMAP5910_ARM_CKCTL
  43 _OMAP5910_ARM_EN_CLK:           .word OMAP5910_ARM_EN_CLK
  44
  45 OMAP5910_MPUI_CTRL:             .word 0x0000ff1b
  46
  47 VAL_EMIFS_CS0_CONFIG:           .word 0x00009090
  48 VAL_EMIFS_CS1_CONFIG:           .word 0x00003031
  49 VAL_EMIFS_CS2_CONFIG:           .word 0x0000a0a1
  50 VAL_EMIFS_CS3_CONFIG:           .word 0x0000c0c0
  51 VAL_EMIFS_DYN_WAIT:             .word 0x00000000
  52 /* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
  53                                 /*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
  54
  55 #if (PHYS_SDRAM_1_SIZE == SZ_32M)
  56 VAL_EMIFF_SDRAM_CONFIG:         .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
  57 #else
  58 VAL_EMIFF_SDRAM_CONFIG:         .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
  59 #endif
  60
  61 VAL_EMIFF_SDRAM_CONFIG2:        .word 0x00000003
  62 VAL_EMIFF_MRS:                  .word 0x00000037
  63
  64 /*
  65  * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
  66  * GPIO07 - LAN91C111 reset
  67  */
  68 GPIO_DIRECTION:
  69         .word 0x0000ff6f
  70 /*
  71  * Disable everything (green LED is connected via invertor)
  72  */
  73 GPIO_OUTPUT:
  74         .word 0x00000010
  75
  76 MUX_CONFIG_BASE:
  77         .word 0xfffe1000
  78
  79 MUX_CONFIG_VALUES:
  80         .align 4
  81         .word 0x00000000        @ FUNC_MUX_CTRL_0
  82         .word 0x00000000        @ FUNC_MUX_CTRL_1
  83         .word 0x00000000        @ FUNC_MUX_CTRL_2
  84         .word 0x00000000        @ FUNC_MUX_CTRL_3
  85         .word 0x00000000        @ FUNC_MUX_CTRL_4
  86         .word 0x02080480        @ FUNC_MUX_CTRL_5
  87         .word 0x0100001c        @ FUNC_MUX_CTRL_6
  88         .word 0x0004800b        @ FUNC_MUX_CTRL_7
  89         .word 0x10001200        @ FUNC_MUX_CTRL_8
  90         .word 0x01201012        @ FUNC_MUX_CTRL_9
  91         .word 0x02082248        @ FUNC_MUX_CTRL_A
  92         .word 0x00000248        @ FUNC_MUX_CTRL_B
  93         .word 0x12240000        @ FUNC_MUX_CTRL_C
  94         .word 0x00002000        @ FUNC_MUX_CTRL_D
  95         .word 0x00000000        @ PULL_DWN_CTRL_0
  96         .word 0x00000800        @ PULL_DWN_CTRL_1
  97         .word 0x01801000        @ PULL_DWN_CTRL_2
  98         .word 0x00000000        @ PULL_DWN_CTRL_3
  99         .word 0x00000000        @ GATE_INH_CTRL_0
 100         .word 0x00000000        @ VOLTAGE_CTRL_0
 101         .word 0x00000000        @ TEST_DBG_CTRL_0
 102         .word 0x00000006        @ MOD_CONF_CTRL_0
 103         .word 0x0000eaef        @ COMP_MODE_CTRL_0
 104
 105 MUX_CONFIG_OFFSETS:
 106         .align 1
 107         .byte 0x00              @ FUNC_MUX_CTRL_0
 108         .byte 0x04              @ FUNC_MUX_CTRL_1
 109         .byte 0x08              @ FUNC_MUX_CTRL_2
 110         .byte 0x10              @ FUNC_MUX_CTRL_3
 111         .byte 0x14              @ FUNC_MUX_CTRL_4
 112         .byte 0x18              @ FUNC_MUX_CTRL_5
 113         .byte 0x1c              @ FUNC_MUX_CTRL_6
 114         .byte 0x20              @ FUNC_MUX_CTRL_7
 115         .byte 0x24              @ FUNC_MUX_CTRL_8
 116         .byte 0x28              @ FUNC_MUX_CTRL_9
 117         .byte 0x2c              @ FUNC_MUX_CTRL_A
 118         .byte 0x30              @ FUNC_MUX_CTRL_B
 119         .byte 0x34              @ FUNC_MUX_CTRL_C
 120         .byte 0x38              @ FUNC_MUX_CTRL_D
 121         .byte 0x40              @ PULL_DWN_CTRL_0
 122         .byte 0x44              @ PULL_DWN_CTRL_1
 123         .byte 0x48              @ PULL_DWN_CTRL_2
 124         .byte 0x4c              @ PULL_DWN_CTRL_3
 125         .byte 0x50              @ GATE_INH_CTRL_0
 126         .byte 0x60              @ VOLTAGE_CTRL_0
 127         .byte 0x70              @ TEST_DBG_CTRL_0
 128         .byte 0x80              @ MOD_CONF_CTRL_0
 129         .byte 0x0c              @ COMP_MODE_CTRL_0
 130         .byte 0xff
 131
 132 .globl platformsetup
 133 platformsetup:
 134         /* Improve performance a bit... */
 135         mrc     p15, 0, r1, c0, c0, 0           @ read C15 ID register
 136         mrc     p15, 0, r1, c0, c0, 1           @ read C15 Cache information register
 137         mrc     p15, 0, r1, c1, c0, 0           @ read C15 Control register
 138         orr     r1, r1, #0x1000                 @ enable I-cache, map interrupt vector 0xffff0000
 139         mcr     p15, 0, r1, c1, c0, 0           @ write C15 Control register
 140         mov     r1, #0x00
 141         mcr     p15, 0, r1, c7, c5, 0           @ Flush I-cache
 142         nop
 143         nop
 144         nop
 145         nop
 146
 147         /* Setup clocking mode */
 148         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ prepare base of CLOCK unit
 149         ldrh    r1, [r0, #0x18]                 @ get reset status
 150         bic     r1, r1, #(7 << 11)              @ clear clock select
 151         orr     r1, r1, #(2 << 11)              @ set synchronous scalable
 152         mov     r2, #0                          @ set wait counter to 100 clock cycles
 153
 154 icache_loop:
 155         cmp     r2, #0x01
 156         streqh  r1, [r0, #0x18]
 157         add     r2, r2, #0x01
 158         cmp     r2, #0x10
 159         bne     icache_loop
 160         nop
 161
 162         /* Setup clock divisors */
 163         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
 164         ldr     r1, _OMAP5910_ARM_CKCTL
 165         orr     r1, r1, #0x2000                 @ enable DSP clock
 166         strh    r1, [r0, #0x00]                 @ setup clock divisors
 167
 168         /* Setup DPLL to generate requested freq */
 169         ldr     r0, OMAP5910_DPLL1_BASE         @ base of DPLL1 register
 170         mov     r1, #0x0010                     @ set PLL_ENABLE
 171         orr     r1, r1, #0x2000                 @ set IOB to new locking
 172         orr     r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
 173         orr     r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
 174         strh    r1, [r0]                        @ write
 175
 176 locking:
 177         ldrh    r1, [r0]                        @ get DPLL value
 178         tst     r1, #0x01
 179         beq     locking                         @ while LOCK not set
 180
 181         /* Enable clock */
 182         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ base of CLOCK unit
 183         mov     r1, #(1 << 10)                  @ disable idle mode do not check
 184                                                 @ nWAKEUP pin, other remain active
 185         strh    r1, [r0, #0x04]
 186         ldr     r1, _OMAP5910_ARM_EN_CLK
 187         strh    r1, [r0, #0x08]
 188         mov     r1, #0x003f                     @ FLASH.RP not enabled in idle and
 189                                                 @ max delayed ( 32 x CLKIN )
 190         strh    r1, [r0, #0x0c]
 191
 192         /* Configure 5910 pins functions to match our board. */
 193         ldr     r0, MUX_CONFIG_BASE
 194         adr     r1, MUX_CONFIG_VALUES
 195         adr     r2, MUX_CONFIG_OFFSETS
 196 next_mux_cfg:
 197         ldrb    r3, [r2], #1
 198         ldr     r4, [r1], #4
 199         cmp     r3, #0xff
 200         strne   r4, [r0, r3]
 201         bne     next_mux_cfg
 202
 203         /* Configure GPIO pins (also disables Green LED) */
 204         ldr     r0, OMAP5910_GPIO_BASE
 205         ldr     r1, GPIO_OUTPUT
 206         strh    r1, [r0, #0x04]
 207         ldr     r1, GPIO_DIRECTION
 208         strh    r1, [r0, #0x08]
 209
 210         /* EnablePeripherals */
 211         ldr     r0, OMAP5910_MPU_CLKM_BASE      @ CLOCK unit
 212         mov     r1, #0x0001                     @ Peripheral enable
 213         strh    r1, [r0, #0x14]
 214
 215         /* Program LED Pulse Generator */
 216         ldr     r0, OMAP5910_LPG1_BASE          @ 1st LED Pulse Generator
 217         mov     r1, #0x7F                       @ Set obscure frequency in
 218         strb    r1, [r0, #0x00]                 @ LCR
 219         mov     r1, #0x01                       @ Enable clock (CLK_EN) in
 220         strb    r1, [r0, #0x04]                 @ PMR
 221
 222         /* TIPB Lock UART1 */
 223         ldr     r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
 224         mov     r1, #1                          @ ARM allocated
 225         strh    r1, [r0,#0x04]                  @ clear IRQ line and status bits
 226         strh    r1, [r0,#0x00]
 227         ldrh    r1, [r0,#0x04]
 228
 229         /* Disable watchdog */
 230         ldr     r0, OMAP5910_MPU_WD_TIMER_BASE
 231         mov     r1, #0xf5
 232         strh    r1, [r0, #0x8]
 233         mov     r1, #0xa0
 234         strh    r1, [r0, #0x8]
 235
 236         /* Enable MCLK */
 237         ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE
 238         mov     r1, #0x6
 239         strh    r1, [r0, #0x34]
 240         strh    r1, [r0, #0x34]
 241
 242         /* Setup clock divisors */
 243         ldr     r0, OMAP5910_ULPD_PWR_MNG_BASE  @ base of ULDPL DPLL1 register
 244
 245         mov     r1, #0x0010                     @ set PLL_ENABLE
 246         orr     r1, r1, #0x2000                 @ set IOB to new locking
 247         strh    r1, [r0]                        @ write
 248
 249 ulocking:
 250         ldrh    r1, [r0]                        @ get DPLL value
 251         tst     r1, #1
 252         beq     ulocking                        @ while LOCK not set
 253
 254         /* EMIF init */
 255         ldr     r0, OMAP5910_MPU_TC_BASE
 256         ldrh    r1, [r0, #0x0c]                 @ EMIFS_CONFIG_REG
 257         bic     r1, r1, #0x0c                   @ pwr down disabled, flash WP
 258         orr     r1, r1, #0x01
 259         str     r1, [r0, #0x0c]
 260
 261         ldr     r1, VAL_EMIFS_CS0_CONFIG
 262         str     r1, [r0, #0x10]                 @ EMIFS_CS0_CONFIG
 263         ldr     r1, VAL_EMIFS_CS1_CONFIG
 264         str     r1, [r0, #0x14]                 @ EMIFS_CS1_CONFIG
 265         ldr     r1, VAL_EMIFS_CS2_CONFIG
 266         str     r1, [r0, #0x18]                 @ EMIFS_CS2_CONFIG
 267         ldr     r1, VAL_EMIFS_CS3_CONFIG
 268         str     r1, [r0, #0x1c]                 @ EMIFS_CS3_CONFIG
 269         ldr     r1, VAL_EMIFS_DYN_WAIT
 270         str     r1, [r0, #0x40]                 @ EMIFS_CFG_DYN_WAIT
 271
 272         /* Setup SDRAM */
 273         ldr     r1, VAL_EMIFF_SDRAM_CONFIG
 274         str     r1, [r0, #0x20]                 @ EMIFF_SDRAM_CONFIG
 275         ldr     r1, VAL_EMIFF_SDRAM_CONFIG2
 276         str     r1, [r0, #0x3c]                 @ EMIFF_SDRAM_CONFIG2
 277         ldr     r1, VAL_EMIFF_MRS
 278         str     r1, [r0, #0x24]                 @ EMIFF_MRS
 279         /* SDRAM needs 100us to stabilize */
 280         mov     r0, #0x4000
 281 sdelay:
 282         subs    r0, r0, #0x1
 283         bne     sdelay
 284
 285         /* back to arch calling code */
 286         mov     pc, lr
 287 .end