]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/netta2/netta2.c
2 * (C) Copyright 2000-2004
3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
27 * U-Boot port on NetTA4 board
35 #ifdef CONFIG_HW_WATCHDOG
39 /****************************************************************/
41 /* some sane bit macros */
42 #define _BD(_b) (1U << (31-(_b)))
43 #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
45 #define _BW(_b) (1U << (15-(_b)))
46 #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
48 #define _BB(_b) (1U << (7-(_b)))
49 #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
51 #define _B(_b) _BD(_b)
52 #define _BR(_l, _h) _BDR(_l, _h)
54 /****************************************************************/
57 * Check Board Identity:
64 printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION
);
68 /****************************************************************/
70 #define _NOT_USED_ 0xFFFFFFFF
72 /****************************************************************/
74 #define CS_0000 0x00000000
75 #define CS_0001 0x10000000
76 #define CS_0010 0x20000000
77 #define CS_0011 0x30000000
78 #define CS_0100 0x40000000
79 #define CS_0101 0x50000000
80 #define CS_0110 0x60000000
81 #define CS_0111 0x70000000
82 #define CS_1000 0x80000000
83 #define CS_1001 0x90000000
84 #define CS_1010 0xA0000000
85 #define CS_1011 0xB0000000
86 #define CS_1100 0xC0000000
87 #define CS_1101 0xD0000000
88 #define CS_1110 0xE0000000
89 #define CS_1111 0xF0000000
91 #define BS_0000 0x00000000
92 #define BS_0001 0x01000000
93 #define BS_0010 0x02000000
94 #define BS_0011 0x03000000
95 #define BS_0100 0x04000000
96 #define BS_0101 0x05000000
97 #define BS_0110 0x06000000
98 #define BS_0111 0x07000000
99 #define BS_1000 0x08000000
100 #define BS_1001 0x09000000
101 #define BS_1010 0x0A000000
102 #define BS_1011 0x0B000000
103 #define BS_1100 0x0C000000
104 #define BS_1101 0x0D000000
105 #define BS_1110 0x0E000000
106 #define BS_1111 0x0F000000
108 #define GPL0_AAAA 0x00000000
109 #define GPL0_AAA0 0x00200000
110 #define GPL0_AAA1 0x00300000
111 #define GPL0_000A 0x00800000
112 #define GPL0_0000 0x00A00000
113 #define GPL0_0001 0x00B00000
114 #define GPL0_111A 0x00C00000
115 #define GPL0_1110 0x00E00000
116 #define GPL0_1111 0x00F00000
118 #define GPL1_0000 0x00000000
119 #define GPL1_0001 0x00040000
120 #define GPL1_1110 0x00080000
121 #define GPL1_1111 0x000C0000
123 #define GPL2_0000 0x00000000
124 #define GPL2_0001 0x00010000
125 #define GPL2_1110 0x00020000
126 #define GPL2_1111 0x00030000
128 #define GPL3_0000 0x00000000
129 #define GPL3_0001 0x00004000
130 #define GPL3_1110 0x00008000
131 #define GPL3_1111 0x0000C000
133 #define GPL4_0000 0x00000000
134 #define GPL4_0001 0x00001000
135 #define GPL4_1110 0x00002000
136 #define GPL4_1111 0x00003000
138 #define GPL5_0000 0x00000000
139 #define GPL5_0001 0x00000400
140 #define GPL5_1110 0x00000800
141 #define GPL5_1111 0x00000C00
142 #define LOOP 0x00000080
144 #define EXEN 0x00000040
146 #define AMX_COL 0x00000000
147 #define AMX_ROW 0x00000020
148 #define AMX_MAR 0x00000030
150 #define NA 0x00000008
152 #define UTA 0x00000004
154 #define TODT 0x00000002
156 #define LAST 0x00000001
158 #define A10_AAAA GPL0_AAAA
159 #define A10_AAA0 GPL0_AAA0
160 #define A10_AAA1 GPL0_AAA1
161 #define A10_000A GPL0_000A
162 #define A10_0000 GPL0_0000
163 #define A10_0001 GPL0_0001
164 #define A10_111A GPL0_111A
165 #define A10_1110 GPL0_1110
166 #define A10_1111 GPL0_1111
168 #define RAS_0000 GPL1_0000
169 #define RAS_0001 GPL1_0001
170 #define RAS_1110 GPL1_1110
171 #define RAS_1111 GPL1_1111
173 #define CAS_0000 GPL2_0000
174 #define CAS_0001 GPL2_0001
175 #define CAS_1110 GPL2_1110
176 #define CAS_1111 GPL2_1111
178 #define WE_0000 GPL3_0000
179 #define WE_0001 GPL3_0001
180 #define WE_1110 GPL3_1110
181 #define WE_1111 GPL3_1111
183 /* #define CAS_LATENCY 3 */
184 #define CAS_LATENCY 2
186 const uint sdram_table
[0x40] = {
190 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
191 CS_1111
| BS_1111
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
192 CS_0000
| BS_1111
| A10_0001
| RAS_1111
| CAS_0001
| WE_1111
| AMX_COL
| UTA
, /* READ */
193 CS_0001
| BS_0001
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
, /* PALL */
194 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
195 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
| TODT
| LAST
, /* NOP */
196 _NOT_USED_
, _NOT_USED_
,
199 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
200 CS_1111
| BS_1111
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
201 CS_0001
| BS_1111
| A10_0001
| RAS_1111
| CAS_0001
| WE_1111
| AMX_COL
| UTA
, /* READ */
202 CS_1111
| BS_0000
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
203 CS_1111
| BS_0000
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
204 CS_1111
| BS_0000
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
205 CS_0001
| BS_0001
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
, /* PALL */
206 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| TODT
| LAST
, /* NOP */
207 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
208 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
211 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
212 CS_1111
| BS_1111
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
213 CS_0000
| BS_0001
| A10_0000
| RAS_1111
| CAS_0001
| WE_0000
| AMX_COL
| UTA
, /* WRITE */
214 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
, /* PALL */
215 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
| TODT
| LAST
, /* NOP */
216 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
219 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
220 CS_1111
| BS_1111
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
221 CS_0001
| BS_0000
| A10_0000
| RAS_1111
| CAS_0001
| WE_0000
| AMX_COL
, /* WRITE */
222 CS_1111
| BS_0000
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
223 CS_1111
| BS_0000
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
224 CS_1111
| BS_0001
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
225 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
226 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
, /* PALL */
227 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
| TODT
| LAST
, /* NOP */
228 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
229 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
234 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
235 CS_1110
| BS_1110
| A10_0000
| RAS_1111
| CAS_1110
| WE_1111
| AMX_COL
| UTA
, /* NOP */
236 CS_0001
| BS_0001
| A10_0000
| RAS_1111
| CAS_0001
| WE_1111
| AMX_COL
| UTA
, /* READ */
237 CS_1110
| BS_1111
| A10_0001
| RAS_1110
| CAS_1111
| WE_1110
| AMX_COL
, /* NOP */
238 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
| TODT
| LAST
, /* PALL */
240 _NOT_USED_
, _NOT_USED_
,
243 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
244 CS_1110
| BS_1110
| A10_0000
| RAS_1111
| CAS_1110
| WE_1111
| AMX_COL
| UTA
, /* NOP */
245 CS_0001
| BS_0000
| A10_0000
| RAS_1111
| CAS_0001
| WE_1111
| AMX_COL
| UTA
, /* READ */
246 CS_1111
| BS_0000
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
247 CS_1111
| BS_0000
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
248 CS_1111
| BS_0001
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
249 CS_1110
| BS_1111
| A10_0001
| RAS_1110
| CAS_1111
| WE_1110
| AMX_COL
, /* NOP */
250 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
| TODT
| LAST
, /* PALL */
252 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
253 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
256 CS_0001
| BS_1111
| A10_AAA0
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
257 CS_1110
| BS_1110
| A10_0000
| RAS_1111
| CAS_1110
| WE_1110
| AMX_COL
, /* NOP */
258 CS_0000
| BS_0001
| A10_0001
| RAS_1110
| CAS_0001
| WE_0000
| AMX_COL
| UTA
, /* WRITE */
259 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
| TODT
| LAST
, /* PALL */
261 _NOT_USED_
, _NOT_USED_
,
265 CS_0001
| BS_1111
| A10_AAAA
| RAS_0001
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* ACT */
266 CS_1110
| BS_1110
| A10_0000
| RAS_1111
| CAS_1110
| WE_1110
| AMX_COL
, /* NOP */
267 CS_0001
| BS_0000
| A10_0000
| RAS_1111
| CAS_0001
| WE_0001
| AMX_COL
, /* WRITE */
268 CS_1111
| BS_0000
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
269 CS_1111
| BS_0000
| A10_0000
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
, /* NOP */
270 CS_1110
| BS_0001
| A10_0001
| RAS_1110
| CAS_1111
| WE_1110
| AMX_COL
| UTA
, /* NOP */
271 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
| TODT
| LAST
, /* PALL */
273 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
274 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
275 _NOT_USED_
, _NOT_USED_
,
280 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_0001
| WE_1111
| AMX_COL
| UTA
| LOOP
, /* ATRFR */
281 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
282 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
283 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
, /* NOP */
284 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
| LOOP
, /* NOP */
285 CS_1111
| BS_1111
| A10_1111
| RAS_1111
| CAS_1111
| WE_1111
| AMX_COL
| UTA
| TODT
| LAST
, /* NOP */
286 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
287 _NOT_USED_
, _NOT_USED_
,
290 CS_0001
| BS_1111
| A10_1111
| RAS_0001
| CAS_1111
| WE_0001
| AMX_COL
| UTA
| LAST
,
294 CS_1110
| BS_1111
| A10_1110
| RAS_1110
| CAS_1110
| WE_1110
| AMX_MAR
| UTA
,
295 CS_0001
| BS_1111
| A10_0001
| RAS_0001
| CAS_0001
| WE_0001
| AMX_MAR
| UTA
| LAST
,
298 #if CONFIG_NETTA2_VERSION == 2
299 static const uint nandcs_table
[0x40] = {
301 CS_1000
| GPL4_1111
| GPL5_1111
| UTA
,
302 CS_0000
| GPL4_1110
| GPL5_1111
| UTA
,
303 CS_0000
| GPL4_0000
| GPL5_1111
| UTA
,
304 CS_0000
| GPL4_0000
| GPL5_1111
| UTA
,
305 CS_0000
| GPL4_0000
| GPL5_1111
,
306 CS_0000
| GPL4_0001
| GPL5_1111
| UTA
,
307 CS_0000
| GPL4_1111
| GPL5_1111
| UTA
,
308 CS_0011
| GPL4_1111
| GPL5_1111
| UTA
| LAST
, /* NOP */
311 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
312 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
313 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
314 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
317 CS_1000
| GPL4_1111
| GPL5_1110
| UTA
,
318 CS_0000
| GPL4_1111
| GPL5_0000
| UTA
,
319 CS_0000
| GPL4_1111
| GPL5_0000
| UTA
,
320 CS_0000
| GPL4_1111
| GPL5_0000
| UTA
,
321 CS_0000
| GPL4_1111
| GPL5_0001
| UTA
,
322 CS_0000
| GPL4_1111
| GPL5_1111
| UTA
,
323 CS_0000
| GPL4_1111
| GPL5_1111
,
324 CS_0011
| GPL4_1111
| GPL5_1111
| UTA
| LAST
,
327 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
328 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
329 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
330 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
333 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
334 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
335 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
347 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
348 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
349 #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
352 #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
353 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
354 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
356 void check_ram(unsigned int addr
, unsigned int size
)
358 unsigned int i
, j
, v
, vv
;
359 volatile unsigned int *p
;
362 p
= (unsigned int *)addr
;
363 pv
= (unsigned int)p
;
364 for (i
= 0; i
< size
/ sizeof(unsigned int); i
++, pv
+= sizeof(unsigned int))
367 p
= (unsigned int *)addr
;
368 for (i
= 0; i
< size
/ sizeof(unsigned int); i
++) {
372 printf("%p: read %08x instead of %08x\n", p
, vv
, v
);
378 for (j
= 0; j
< 5; j
++) {
380 case 0: v
= 0x00000000; break;
381 case 1: v
= 0xffffffff; break;
382 case 2: v
= 0x55555555; break;
383 case 3: v
= 0xaaaaaaaa; break;
384 default:v
= 0xdeadbeef; break;
386 p
= (unsigned int *)addr
;
387 for (i
= 0; i
< size
/ sizeof(unsigned int); i
++) {
391 printf("%p: read %08x instead of %08x\n", p
, vv
, v
);
400 long int initdram(int board_type
)
402 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
403 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
406 upmconfig(UPMB
, (uint
*) sdram_table
, sizeof(sdram_table
) / sizeof(sdram_table
[0]));
409 * Preliminary prescaler for refresh
411 memctl
->memc_mptpr
= MPTPR_PTP_DIV8
;
413 memctl
->memc_mar
= MAR_SDRAM_INIT
; /* 32-bit address to be output on the address bus if AMX = 0b11 */
416 * Map controller bank 3 to the SDRAM bank at preliminary address.
418 memctl
->memc_or3
= CFG_OR3_PRELIM
;
419 memctl
->memc_br3
= CFG_BR3_PRELIM
;
421 memctl
->memc_mbmr
= CFG_MAMR
& ~MAMR_PTAE
; /* no refresh yet */
425 /* perform SDRAM initialisation sequence */
426 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS3
| MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
429 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS3
| MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
432 memctl
->memc_mcr
= MCR_OP_RUN
| MCR_UPM_B
| MCR_MB_CS3
| MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
435 memctl
->memc_mbmr
|= MAMR_PTAE
; /* enable refresh */
443 *(volatile u32
*)0 = d1
;
444 d2
= *(volatile u32
*)0;
446 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1
, d2
);
451 *(volatile u32
*)0 = d1
;
452 d2
= *(volatile u32
*)0;
454 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1
, d2
);
459 size
= get_ram_size((long *)0, SDRAM_MAX_SIZE
);
462 printf("SIZE is zero: LOOP on 0\n");
464 *(volatile u32
*)0 = 0;
465 (void)*(volatile u32
*)0;
472 /* ------------------------------------------------------------------------- */
474 void reset_phys(void)
480 /* reset the damn phys */
483 for (phyno
= 0; phyno
< 32; ++phyno
) {
484 miiphy_read(phyno
, PHY_PHYIDR1
, &v
);
487 miiphy_write(phyno
, PHY_BMCR
, PHY_BMCR_POWD
);
489 miiphy_write(phyno
, PHY_BMCR
, PHY_BMCR_RESET
| PHY_BMCR_AUTON
);
494 /* ------------------------------------------------------------------------- */
496 /* GP = general purpose, SP = special purpose (on chip peripheral) */
498 /* bits that can have a special purpose or can be configured as inputs/outputs */
499 #define PA_GP_INMASK 0
500 #define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
503 #define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
504 #define PA_SP_DIRVAL 0
506 #define PB_GP_INMASK _B(28)
507 #define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
508 #define PB_SP_MASK (_BR(22, 25))
510 #define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
511 #define PB_SP_DIRVAL 0
513 #if CONFIG_NETTA2_VERSION == 1
514 #define PC_GP_INMASK _BW(12)
515 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
516 #elif CONFIG_NETTA2_VERSION == 2
517 #define PC_GP_INMASK (_BW(13) | _BW(15))
518 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
523 #define PC_GP_OUTVAL (_BW(10) | _BW(11))
524 #define PC_SP_DIRVAL 0
526 #if CONFIG_NETTA2_VERSION == 1
527 #define PE_GP_INMASK _B(31)
528 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
529 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
530 #elif CONFIG_NETTA2_VERSION == 2
531 #define PE_GP_INMASK _BR(28, 31)
532 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
533 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
537 #define PE_SP_DIRVAL 0
539 int board_early_init_f(void)
541 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
542 volatile iop8xx_t
*ioport
= &immap
->im_ioport
;
543 volatile cpm8xx_t
*cpm
= &immap
->im_cpm
;
544 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
546 /* NAND chip select */
547 #if CONFIG_NETTA2_VERSION == 1
548 memctl
->memc_or1
= ((0xFFFFFFFFLU
& ~(NAND_SIZE
- 1)) | OR_CSNT_SAM
| OR_BI
| OR_SCY_8_CLK
| OR_EHTR
| OR_TRLX
);
549 memctl
->memc_br1
= ((NAND_BASE
& BR_BA_MSK
) | BR_PS_8
| BR_V
);
550 #elif CONFIG_NETTA2_VERSION == 2
551 upmconfig(UPMA
, (uint
*) nandcs_table
, sizeof(nandcs_table
) / sizeof(nandcs_table
[0]));
552 memctl
->memc_or1
= ((0xFFFFFFFFLU
& ~(NAND_SIZE
- 1)) | OR_BI
| OR_G5LS
);
553 memctl
->memc_br1
= ((NAND_BASE
& BR_BA_MSK
) | BR_PS_8
| BR_V
| BR_MS_UPMA
);
554 memctl
->memc_mamr
= 0; /* all clear */
557 /* DSP chip select */
558 memctl
->memc_or2
= ((0xFFFFFFFFLU
& ~(DSP_SIZE
- 1)) | OR_CSNT_SAM
| OR_BI
| OR_ACS_DIV2
| OR_SETA
| OR_TRLX
);
559 memctl
->memc_br2
= ((DSP_BASE
& BR_BA_MSK
) | BR_PS_16
| BR_V
);
561 #if CONFIG_NETTA2_VERSION == 1
562 memctl
->memc_br4
&= ~BR_V
;
564 memctl
->memc_br5
&= ~BR_V
;
565 memctl
->memc_br6
&= ~BR_V
;
566 memctl
->memc_br7
&= ~BR_V
;
568 ioport
->iop_padat
= PA_GP_OUTVAL
;
569 ioport
->iop_paodr
= PA_ODR_VAL
;
570 ioport
->iop_padir
= PA_GP_OUTMASK
| PA_SP_DIRVAL
;
571 ioport
->iop_papar
= PA_SP_MASK
;
573 cpm
->cp_pbdat
= PB_GP_OUTVAL
;
574 cpm
->cp_pbodr
= PB_ODR_VAL
;
575 cpm
->cp_pbdir
= PB_GP_OUTMASK
| PB_SP_DIRVAL
;
576 cpm
->cp_pbpar
= PB_SP_MASK
;
578 ioport
->iop_pcdat
= PC_GP_OUTVAL
;
579 ioport
->iop_pcdir
= PC_GP_OUTMASK
| PC_SP_DIRVAL
;
580 ioport
->iop_pcso
= PC_SOVAL
;
581 ioport
->iop_pcint
= PC_INTVAL
;
582 ioport
->iop_pcpar
= PC_SP_MASK
;
584 cpm
->cp_pedat
= PE_GP_OUTVAL
;
585 cpm
->cp_peodr
= PE_ODR_VAL
;
586 cpm
->cp_pedir
= PE_GP_OUTMASK
| PE_SP_DIRVAL
;
587 cpm
->cp_pepar
= PE_SP_MASK
;
592 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
594 #include <linux/mtd/nand.h>
596 extern ulong
nand_probe(ulong physadr
);
597 extern struct nand_chip nand_dev_desc
[CFG_MAX_NAND_DEVICE
];
601 unsigned long totlen
;
603 totlen
= nand_probe(CFG_NAND_BASE
);
604 printf ("%4lu MB\n", totlen
>> 20);
608 #ifdef CONFIG_HW_WATCHDOG
610 void hw_watchdog_reset(void)
612 /* XXX add here the really funky stuff */
617 #ifdef CONFIG_SHOW_ACTIVITY
619 /* called from timer interrupt every 1/CFG_HZ sec */
620 void board_show_activity(ulong timestamp
)
624 /* called when looping */
625 void show_activity(int arg
)
631 #if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
632 int overwrite_console(void)
634 /* printf("overwrite_console called\n"); */
639 extern int drv_phone_init(void);
640 extern int drv_phone_use_me(void);
641 extern int drv_phone_is_idle(void);
643 int misc_init_r(void)
648 int last_stage_init(void)
650 #if CONFIG_NETTA2_VERSION == 2
654 #if CONFIG_NETTA2_VERSION == 2
655 /* assert peripheral reset */
656 ((volatile immap_t
*)CFG_IMMR
)->im_ioport
.iop_pcdat
&= ~_BW(12);
657 for (i
= 0; i
< 10; i
++)
659 ((volatile immap_t
*)CFG_IMMR
)->im_ioport
.iop_pcdat
|= _BW(12);