board/nvidia/cardhu/pinmux-config-cardhu.h

   1 /*
   2  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef _PINMUX_CONFIG_CARDHU_H_
  18 #define _PINMUX_CONFIG_CARDHU_H_
  19
  20 #define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)       \
  21         {                                                       \
  22                 .pingroup       = PINGRP_##_pingroup,           \
  23                 .func           = PMUX_FUNC_##_mux,             \
  24                 .pull           = PMUX_PULL_##_pull,            \
  25                 .tristate       = PMUX_TRI_##_tri,              \
  26                 .io             = PMUX_PIN_##_io,               \
  27                 .lock           = PMUX_PIN_LOCK_DEFAULT,        \
  28                 .od             = PMUX_PIN_OD_DEFAULT,          \
  29                 .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
  30         }
  31
  32 #define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
  33         {                                                       \
  34                 .pingroup       = PINGRP_##_pingroup,           \
  35                 .func           = PMUX_FUNC_##_mux,             \
  36                 .pull           = PMUX_PULL_##_pull,            \
  37                 .tristate       = PMUX_TRI_##_tri,              \
  38                 .io             = PMUX_PIN_##_io,               \
  39                 .lock           = PMUX_PIN_LOCK_##_lock,        \
  40                 .od             = PMUX_PIN_OD_##_od,            \
  41                 .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
  42         }
  43
  44 #define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
  45         {                                                       \
  46                 .pingroup       = PINGRP_##_pingroup,           \
  47                 .func           = PMUX_FUNC_##_mux,             \
  48                 .pull           = PMUX_PULL_##_pull,            \
  49                 .tristate       = PMUX_TRI_##_tri,              \
  50                 .io             = PMUX_PIN_##_io,               \
  51                 .lock           = PMUX_PIN_LOCK_##_lock,        \
  52                 .od             = PMUX_PIN_OD_DEFAULT,          \
  53                 .ioreset        = PMUX_PIN_IO_RESET_##_ioreset  \
  54         }
  55
  56 #define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
  57         {                                                       \
  58                 .padgrp         = PDRIVE_PINGROUP_##_padgrp,    \
  59                 .slwf           = _slwf,                        \
  60                 .slwr           = _slwr,                        \
  61                 .drvup          = _drvup,                       \
  62                 .drvdn          = _drvdn,                       \
  63                 .lpmd           = PGRP_LPMD_##_lpmd,            \
  64                 .schmt          = PGRP_SCHMT_##_schmt,          \
  65                 .hsm            = PGRP_HSM_##_hsm,              \
  66         }
  67
  68 static struct pingroup_config tegra3_pinmux_common[] = {
  69         /* SDMMC1 pinmux */
  70         DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
  71         DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
  72         DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
  73         DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
  74         DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
  75         DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
  76
  77         /* SDMMC3 pinmux */
  78         DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
  79         DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
  80         DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
  81         DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
  82         DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
  83         DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
  84         DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
  85         DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
  86
  87         /* SDMMC4 pinmux */
  88         LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
  89         LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  90         LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  91         LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  92         LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  93         LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  94         LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  95         LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  96         LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  97         LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
  98         LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
  99
 100         /* I2C1 pinmux */
 101         I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 102         I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 103
 104         /* I2C2 pinmux */
 105         I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 106         I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 107
 108         /* I2C3 pinmux */
 109         I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 110         I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 111
 112         /* I2C4 pinmux */
 113         I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 114         I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 115
 116         /* Power I2C pinmux */
 117         I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 118         I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
 119
 120         DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
 121         DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
 122         DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
 123         DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
 124         DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
 125         DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
 126         DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
 127         DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
 128         DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
 129         DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
 130         DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
 131         DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
 132         DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
 133         DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
 134         DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
 135         DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
 136         DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
 137         DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
 138         DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
 139         DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
 140         DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
 141         DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
 142         DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
 143         DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
 144         DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
 145         DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
 146         DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
 147         DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
 148         DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
 149         DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
 150         DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
 151         DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
 152         DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
 153         DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
 154         DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
 155         DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
 156         DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
 157         DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
 158         DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
 159         DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
 160         DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
 161         DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
 162         DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
 163         DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
 164         DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
 165         DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
 166         DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
 167         DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
 168         DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
 169         DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
 170         DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
 171         DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
 172         DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
 173         DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
 174         DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
 175         DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
 176         DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
 177         DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
 178         DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
 179         DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
 180         DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
 181         DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
 182         LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 183         LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 184         LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 185         LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 186         LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
 187         LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 188         LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 189         LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 190         LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
 191         DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
 192         DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
 193         DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
 194         DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
 195         DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
 196         DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
 197         DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
 198         DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
 199         DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
 200         DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
 201         DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
 202         DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
 203         DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
 204         DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
 205         DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
 206         DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
 207         DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
 208         DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
 209         DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
 210         DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
 211         DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
 212         DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
 213         DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
 214         DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
 215         DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
 216         DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
 217         DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
 218         DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
 219         DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
 220         DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
 221         DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
 222         DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
 223         DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
 224         DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
 225         DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
 226         DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
 227         DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
 228         DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
 229
 230         /* KBC keys */
 231         DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
 232         DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
 233         DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
 234         DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
 235         DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
 236         DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
 237         DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
 238         DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
 239         DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
 240         DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
 241         DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
 242         DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
 243         DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
 244         DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
 245         DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
 246         DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
 247         DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
 248         DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
 249         DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
 250         DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
 251         DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
 252         DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
 253         DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
 254         DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
 255         DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
 256
 257         DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
 258         DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
 259         DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
 260         DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
 261         DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
 262         DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
 263         DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
 264         DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
 265         DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
 266         DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
 267         DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
 268         DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
 269         DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
 270         DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
 271         DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
 272
 273         DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
 274         DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
 275         DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
 276         DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
 277         DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
 278         DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
 279         DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
 280         DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
 281         DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
 282         DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
 283         DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
 284         DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
 285         DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
 286         DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
 287         DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
 288         DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
 289         DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
 290
 291         /* GPIOs */
 292         /* SDMMC1 CD gpio */
 293         DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
 294         /* SDMMC1 WP gpio */
 295         LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
 296
 297         /* Touch panel GPIO */
 298         /* Touch IRQ */
 299         DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
 300
 301         /* Touch RESET */
 302         DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
 303
 304         /* Power rails GPIO */
 305         DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
 306         DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
 307         DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
 308         DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
 309         DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
 310
 311         LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
 312         LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 313         LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 314         LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
 315         LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 316         LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
 317 };
 318
 319 static struct pingroup_config unused_pins_lowpower[] = {
 320         DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
 321         DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
 322         DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
 323         DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
 324         DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
 325         DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
 326         DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
 327         DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
 328         DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
 329         DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
 330         DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
 331         DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
 332         DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
 333         DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
 334         DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
 335         DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
 336         DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
 337         DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
 338         DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
 339 };
 340
 341 static struct padctrl_config cardhu_padctrl[] = {
 342         /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
 343         DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
 344                 SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
 345 };
 346 #endif  /* _PINMUX_CONFIG_CARDHU_H_ */