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[people/ms/u-boot.git] / board / omap2420h4 / omap2420h4.c
1 /*
2 * (C) Copyright 2004
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24 #include <common.h>
25 #include <asm/arch/omap2420.h>
26 #include <asm/io.h>
27 #include <asm/arch/bits.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/mem.h>
32 #include <i2c.h>
33 #include <asm/mach-types.h>
34 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
35 #include <linux/mtd/nand.h>
36 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
37 #endif
38
39 static void wait_for_command_complete(unsigned int wd_base);
40
41 /*******************************************************
42 * Routine: delay
43 * Description: spinning delay to use before udelay works
44 ******************************************************/
45 static inline void delay (unsigned long loops)
46 {
47 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
48 "bne 1b":"=r" (loops):"0" (loops));
49 }
50
51 /*****************************************
52 * Routine: board_init
53 * Description: Early hardware init.
54 *****************************************/
55 int board_init (void)
56 {
57 DECLARE_GLOBAL_DATA_PTR;
58
59 gpmc_init(); /* in SRAM or SDRM, finish GPMC */
60
61 gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
62 gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
63
64 return 0;
65 }
66
67 /**********************************************************
68 * Routine: try_unlock_sram()
69 * Description: If chip is GP type, unlock the SRAM for
70 * general use.
71 ***********************************************************/
72 void try_unlock_sram(void)
73 {
74 int mode;
75
76 /* if GP device unlock device SRAM for general use */
77 mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
78 if (mode == GP_DEVICE) {
79 __raw_writel(0xFF, A_REQINFOPERM0);
80 __raw_writel(0xCFDE, A_READPERM0);
81 __raw_writel(0xCFDE, A_WRITEPERM0);
82 }
83 }
84
85 /**********************************************************
86 * Routine: s_init
87 * Description: Does early system init of muxing and clocks.
88 * - Called path is with sram stack.
89 **********************************************************/
90 void s_init(void)
91 {
92 int in_sdram = running_in_sdram();
93
94 watchdog_init();
95 set_muxconf_regs();
96 delay(100);
97 try_unlock_sram();
98
99 if(!in_sdram)
100 prcm_init();
101
102 peripheral_enable();
103 icache_enable();
104 if (!in_sdram)
105 sdrc_init();
106 }
107
108 /*******************************************************
109 * Routine: misc_init_r
110 * Description: Init ethernet (done here so udelay works)
111 ********************************************************/
112 int misc_init_r (void)
113 {
114 ether_init(); /* better done here so timers are init'ed */
115 return(0);
116 }
117
118 /****************************************
119 * Routine: watchdog_init
120 * Description: Shut down watch dogs
121 *****************************************/
122 void watchdog_init(void)
123 {
124 /* There are 4 watch dogs. 1 secure, and 3 general purpose.
125 * The ROM takes care of the secure one. Of the 3 GP ones,
126 * 1 can reset us directly, the other 2 only generate MPU interrupts.
127 */
128 __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
129 wait_for_command_complete(WD2_BASE);
130 __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
131
132 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
133 __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
134 wait_for_command_complete(WD3_BASE);
135 __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
136
137 __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
138 wait_for_command_complete(WD4_BASE);
139 __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
140 #endif
141 }
142
143 /******************************************************
144 * Routine: wait_for_command_complete
145 * Description: Wait for posting to finish on watchdog
146 ******************************************************/
147 static void wait_for_command_complete(unsigned int wd_base)
148 {
149 int pending = 1;
150 do {
151 pending = __raw_readl(wd_base+WWPS);
152 } while (pending);
153 }
154
155 /*******************************************************************
156 * Routine:ether_init
157 * Description: take the Ethernet controller out of reset and wait
158 * for the EEPROM load to complete.
159 ******************************************************************/
160 void ether_init (void)
161 {
162 #ifdef CONFIG_DRIVER_LAN91C96
163 int cnt = 20;
164
165 __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
166
167 __raw_writew(0x0, LAN_RESET_REGISTER);
168 do {
169 __raw_writew(0x1, LAN_RESET_REGISTER);
170 udelay (100);
171 if (cnt == 0)
172 goto h4reset_err_out;
173 --cnt;
174 } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
175
176 cnt = 20;
177
178 do {
179 __raw_writew(0x0, LAN_RESET_REGISTER);
180 udelay (100);
181 if (cnt == 0)
182 goto h4reset_err_out;
183 --cnt;
184 } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
185 udelay (1000);
186
187 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
188 udelay (1000);
189
190 h4reset_err_out:
191 return;
192 #endif
193 }
194
195 /**********************************************
196 * Routine: dram_init
197 * Description: sets uboots idea of sdram size
198 **********************************************/
199 int dram_init (void)
200 {
201 DECLARE_GLOBAL_DATA_PTR;
202 unsigned int size0=0,size1=0;
203 u32 mtype, btype;
204 u8 chg_on = 0x5; /* enable charge of back up battery */
205 u8 vmode_on = 0x8C;
206 #define NOT_EARLY 0
207
208 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
209
210 btype = get_board_type();
211 mtype = get_mem_type();
212
213 display_board_info(btype);
214 if (btype == BOARD_H4_MENELAUS){
215 update_mux(btype,mtype); /* combo part on menelaus */
216 i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
217 i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
218 }
219
220 if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
221 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
222 size0 = size1 = SZ_32M;
223 } else if (mtype == SDR_DISCRETE)
224 size0 = SZ_128M;
225 else
226 size0 = SZ_64M;
227
228 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
229 gd->bd->bi_dram[0].size = size0;
230 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
231 gd->bd->bi_dram[1].size = size1;
232
233 return 0;
234 }
235
236 /**********************************************************
237 * Routine: set_muxconf_regs
238 * Description: Setting up the configuration Mux registers
239 * specific to the hardware
240 *********************************************************/
241 void set_muxconf_regs (void)
242 {
243 muxSetupSDRC();
244 muxSetupGPMC();
245 muxSetupUsb0();
246 muxSetupUart3();
247 muxSetupI2C1();
248 muxSetupUART1();
249 muxSetupLCD();
250 muxSetupCamera();
251 muxSetupMMCSD();
252 muxSetupTouchScreen();
253 muxSetupHDQ();
254 }
255
256 /*****************************************************************
257 * Routine: peripheral_enable
258 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
259 ******************************************************************/
260 void peripheral_enable(void)
261 {
262 unsigned int v, if_clks=0, func_clks=0;
263
264 /* Enable GP2 timer.*/
265 if_clks |= BIT4;
266 func_clks |= BIT4;
267 v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
268 __raw_writel(v, CM_CLKSEL2_CORE);
269 __raw_writel(0x1, CM_CLKSEL_WKUP);
270
271 #ifdef CFG_NS16550
272 /* Enable UART1 clock */
273 func_clks |= BIT21;
274 if_clks |= BIT21;
275 #endif
276 v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
277 __raw_writel(v,CM_ICLKEN1_CORE );
278 v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
279 __raw_writel(v, CM_FCLKEN1_CORE);
280 delay(1000);
281
282 #ifndef KERNEL_UPDATED
283 {
284 #define V1 0xffffffff
285 #define V2 0x00000007
286
287 __raw_writel(V1, CM_FCLKEN1_CORE);
288 __raw_writel(V2, CM_FCLKEN2_CORE);
289 __raw_writel(V1, CM_ICLKEN1_CORE);
290 __raw_writel(V1, CM_ICLKEN2_CORE);
291 }
292 #endif
293 }
294
295 /****************************************
296 * Routine: muxSetupUsb0 (ostboot)
297 * Description: Setup usb muxing
298 *****************************************/
299 void muxSetupUsb0(void)
300 {
301 volatile uint8 *MuxConfigReg;
302 volatile uint32 *otgCtrlReg;
303
304 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
305 *MuxConfigReg &= (uint8)(~0x1F);
306
307 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
308 *MuxConfigReg &= (uint8)(~0x1F);
309
310 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
311 *MuxConfigReg &= (uint8)(~0x1F);
312
313 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
314 *MuxConfigReg &= (uint8)(~0x1F);
315
316 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
317 *MuxConfigReg &= (uint8)(~0x1F);
318
319 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
320 *MuxConfigReg &= (uint8)(~0x1F);
321
322 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
323 *MuxConfigReg &= (uint8)(~0x1F);
324
325 /* setup for USB VBus detection */
326 otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
327 *otgCtrlReg |= 0x00040000; /* bit 18 */
328 }
329
330 /****************************************
331 * Routine: muxSetupUart3 (ostboot)
332 * Description: Setup uart3 muxing
333 *****************************************/
334 void muxSetupUart3(void)
335 {
336 volatile uint8 *MuxConfigReg;
337
338 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
339 *MuxConfigReg &= (uint8)(~0x1F);
340
341 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
342 *MuxConfigReg &= (uint8)(~0x1F);
343 }
344
345 /****************************************
346 * Routine: muxSetupI2C1 (ostboot)
347 * Description: Setup i2c muxing
348 *****************************************/
349 void muxSetupI2C1(void)
350 {
351 volatile unsigned char *MuxConfigReg;
352
353 /* I2C1 Clock pin configuration, PIN = M19 */
354 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
355 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
356
357 /* I2C1 Data pin configuration, PIN = L15 */
358 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
359 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
360
361 /* Pull-up required on data line */
362 /* external pull-up already present. */
363 /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
364 }
365
366 /****************************************
367 * Routine: muxSetupUART1 (ostboot)
368 * Description: Set up uart1 muxing
369 *****************************************/
370 void muxSetupUART1(void)
371 {
372 volatile unsigned char *MuxConfigReg;
373
374 /* UART1_CTS pin configuration, PIN = D21 */
375 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
376 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
377
378 /* UART1_RTS pin configuration, PIN = H21 */
379 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
380 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
381
382 /* UART1_TX pin configuration, PIN = L20 */
383 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
384 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
385
386 /* UART1_RX pin configuration, PIN = T21 */
387 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
388 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
389 }
390
391 /****************************************
392 * Routine: muxSetupLCD (ostboot)
393 * Description: Setup lcd muxing
394 *****************************************/
395 void muxSetupLCD(void)
396 {
397 volatile unsigned char *MuxConfigReg;
398
399 /* LCD_D0 pin configuration, PIN = Y7 */
400 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
401 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
402
403 /* LCD_D1 pin configuration, PIN = P10 */
404 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
405 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
406
407 /* LCD_D2 pin configuration, PIN = V8 */
408 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
409 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
410
411 /* LCD_D3 pin configuration, PIN = Y8 */
412 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
413 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
414
415 /* LCD_D4 pin configuration, PIN = W8 */
416 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
417 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
418
419 /* LCD_D5 pin configuration, PIN = R10 */
420 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
421 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
422
423 /* LCD_D6 pin configuration, PIN = Y9 */
424 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
425 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
426
427 /* LCD_D7 pin configuration, PIN = V9 */
428 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
429 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
430
431 /* LCD_D8 pin configuration, PIN = W9 */
432 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
433 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
434
435 /* LCD_D9 pin configuration, PIN = P11 */
436 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
437 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
438
439 /* LCD_D10 pin configuration, PIN = V10 */
440 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
441 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
442
443 /* LCD_D11 pin configuration, PIN = Y10 */
444 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
445 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
446
447 /* LCD_D12 pin configuration, PIN = W10 */
448 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
449 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
450
451 /* LCD_D13 pin configuration, PIN = R11 */
452 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
453 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
454
455 /* LCD_D14 pin configuration, PIN = V11 */
456 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
457 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
458
459 /* LCD_D15 pin configuration, PIN = W11 */
460 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
461 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
462
463 /* LCD_D16 pin configuration, PIN = P12 */
464 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
465 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
466
467 /* LCD_D17 pin configuration, PIN = R12 */
468 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
469 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
470
471 /* LCD_PCLK pin configuration, PIN = W6 */
472 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
473 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
474
475 /* LCD_VSYNC pin configuration, PIN = V7 */
476 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
477 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
478
479 /* LCD_HSYNC pin configuration, PIN = Y6 */
480 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
481 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
482
483 /* LCD_ACBIAS pin configuration, PIN = W7 */
484 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
485 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
486 }
487
488 /****************************************
489 * Routine: muxSetupCamera (ostboot)
490 * Description: Setup camera muxing
491 *****************************************/
492 void muxSetupCamera(void)
493 {
494 volatile unsigned char *MuxConfigReg;
495
496 /* CAMERA_RSTZ pin configuration, PIN = Y16 */
497 /* CAM_RST is connected through the I2C IO expander.*/
498 /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
499 /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
500
501 /* CAMERA_XCLK pin configuration, PIN = U3 */
502 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
503 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
504
505 /* CAMERA_LCLK pin configuration, PIN = V5 */
506 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
507 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
508
509 /* CAMERA_VSYNC pin configuration, PIN = U2 */
510 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
511 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
512
513 /* CAMERA_HSYNC pin configuration, PIN = T3 */
514 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
515 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
516
517 /* CAMERA_DAT0 pin configuration, PIN = T4 */
518 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
519 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
520
521 /* CAMERA_DAT1 pin configuration, PIN = V2 */
522 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
523 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
524
525 /* CAMERA_DAT2 pin configuration, PIN = V3 */
526 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
527 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
528
529 /* CAMERA_DAT3 pin configuration, PIN = U4 */
530 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
531 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
532
533 /* CAMERA_DAT4 pin configuration, PIN = W2 */
534 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
535 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
536
537 /* CAMERA_DAT5 pin configuration, PIN = V4 */
538 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
539 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
540
541 /* CAMERA_DAT6 pin configuration, PIN = W3 */
542 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
543 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
544
545 /* CAMERA_DAT7 pin configuration, PIN = Y2 */
546 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
547 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
548
549 /* CAMERA_DAT8 pin configuration, PIN = Y4 */
550 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
551 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
552
553 /* CAMERA_DAT9 pin configuration, PIN = V6 */
554 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
555 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
556 }
557
558 /****************************************
559 * Routine: muxSetupMMCSD (ostboot)
560 * Description: set up MMC muxing
561 *****************************************/
562 void muxSetupMMCSD(void)
563 {
564 volatile unsigned char *MuxConfigReg;
565
566 /* SDMMC_CLKI pin configuration, PIN = H15 */
567 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
568 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
569
570 /* SDMMC_CLKO pin configuration, PIN = G19 */
571 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
572 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
573
574 /* SDMMC_CMD pin configuration, PIN = H18 */
575 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
576 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
577 /* External pull-ups are present. */
578 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
579
580 /* SDMMC_DAT0 pin configuration, PIN = F20 */
581 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
582 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
583 /* External pull-ups are present. */
584 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
585
586 /* SDMMC_DAT1 pin configuration, PIN = H14 */
587 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
588 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
589 /* External pull-ups are present. */
590 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
591
592 /* SDMMC_DAT2 pin configuration, PIN = E19 */
593 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
594 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
595 /* External pull-ups are present. */
596 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
597
598 /* SDMMC_DAT3 pin configuration, PIN = D19 */
599 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
600 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
601 /* External pull-ups are present. */
602 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
603
604 /* SDMMC_DDIR0 pin configuration, PIN = F19 */
605 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
606 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
607
608 /* SDMMC_DDIR1 pin configuration, PIN = E20 */
609 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
610 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
611
612 /* SDMMC_DDIR2 pin configuration, PIN = F18 */
613 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
614 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
615
616 /* SDMMC_DDIR3 pin configuration, PIN = E18 */
617 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
618 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
619
620 /* SDMMC_CDIR pin configuration, PIN = G18 */
621 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
622 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
623
624 /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
625 /* MMC_CD for 2422IP=K1 */
626 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
627 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
628
629 /* MMC_WP pin configuration, PIN = B4 */
630 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
631 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
632 }
633
634 /******************************************
635 * Routine: muxSetupTouchScreen (ostboot)
636 * Description: Set up touch screen muxing
637 *******************************************/
638 void muxSetupTouchScreen(void)
639 {
640 volatile unsigned char *MuxConfigReg;
641
642 /* SPI1_CLK pin configuration, PIN = U18 */
643 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
644 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
645
646 /* SPI1_MOSI pin configuration, PIN = V20 */
647 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
648 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
649
650 /* SPI1_MISO pin configuration, PIN = T18 */
651 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
652 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
653
654 /* SPI1_nCS0 pin configuration, PIN = U19 */
655 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
656 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
657
658 /* PEN_IRQ pin configuration, PIN = P20 */
659 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
660 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
661 }
662
663 /****************************************
664 * Routine: muxSetupHDQ (ostboot)
665 * Description: setup 1wire mux
666 *****************************************/
667 void muxSetupHDQ(void)
668 {
669 volatile unsigned char *MuxConfigReg;
670
671 /* HDQ_SIO pin configuration, PIN = N18 */
672 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
673 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
674 }
675
676 /***************************************************************
677 * Routine: muxSetupGPMC (ostboot)
678 * Description: Configures balls which cam up in protected mode
679 ***************************************************************/
680 void muxSetupGPMC(void)
681 {
682 volatile uint8 *MuxConfigReg;
683 volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
684
685 /* gpmc_io_dir */
686 *MCR = 0x19000000;
687
688 /* NOR FLASH CS0 */
689 /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
690 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
691 *MuxConfigReg = 0x00 ;
692
693 /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */
694 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
695 *MuxConfigReg = 0x01 ;
696
697 /* MPDB(Multi Port Debug Port) CS1 */
698 /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
699 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
700 *MuxConfigReg = 0x00 ;
701
702 /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
703 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
704 *MuxConfigReg = 0x00 ;
705 }
706
707 /****************************************************************
708 * Routine: muxSetupSDRC (ostboot)
709 * Description: Configures balls which come up in protected mode
710 ****************************************************************/
711 void muxSetupSDRC(void)
712 {
713 volatile uint8 *MuxConfigReg;
714
715 /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */
716 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
717 *MuxConfigReg = 0x00 ;
718
719 /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */
720 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
721 *MuxConfigReg = 0x00 ;
722
723 /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */
724 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
725 *MuxConfigReg = 0x00;
726
727 if (get_cpu_type() == CPU_2422) {
728 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
729 *MuxConfigReg = 0x1b;
730 }
731 }
732
733 /*****************************************************************************
734 * Routine: update_mux()
735 * Description: Update balls which are different beween boards. All should be
736 * updated to match functionaly. However, I'm only updating ones
737 * which I'll be using for now. When power comes into play they
738 * all need updating.
739 *****************************************************************************/
740 void update_mux(u32 btype,u32 mtype)
741 {
742 u32 cpu, base = OMAP2420_CTRL_BASE;
743 cpu = get_cpu_type();
744
745 if (btype == BOARD_H4_MENELAUS) {
746 if (cpu == CPU_2420) {
747 /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/
748 __raw_writeb(0x3, base+0x30);
749 /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/
750 __raw_writeb(0x3, base+0xa3);
751 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
752 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
753 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
754 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
755 /* PIN = M1 (HSUSBOTG) */
756 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
757 __raw_writeb(0x3, base+0x9d);
758 /* PIN = U32, (WLAN_CLKREQ) */
759 /* PIN = Y11, WLAN */
760 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
761 __raw_writeb(0x3, base+0xe7);
762 /* PIN = AA8, mDOC */
763 /* PIN = AA10, BT */
764 /* PIN = AA13, WLAN */
765 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
766 __raw_writeb(0x3, base+0x10e);
767 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
768 __raw_writeb(0x3, base+0x110);
769 /* PIN = J15 HHUSB */
770 /* PIN = H19 HSUSB */
771 /* PIN = W13, P13, R13, W16 ... */
772 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
773 __raw_writeb(0x3, base+0xde);
774 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
775 __raw_writeb(0x0, base+0x12c);
776 /* PIN = AA17->sys_clkreq mode 0 -DO- */
777 __raw_writeb(0x0, base+0x136);
778 } else if (cpu == CPU_2422) {
779 /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/
780 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
781 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
782 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
783 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
784 __raw_writeb(0x0, base+0x92);
785 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
786 /* PIN = M1 (HSUSBOTG) */
787 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
788 __raw_writeb(0x3, base+0x10c);
789 /* PIN = U32, (WLAN_CLKREQ) */
790 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
791 __raw_writeb(0x3, base+0x30);
792 /* PIN = AA8, mDOC */
793 /* PIN = AA10, BT */
794 /* PIN = AA12, WLAN */
795 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
796 __raw_writeb(0x3, base+0x10e);
797 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
798 __raw_writeb(0x3, base+0x110);
799 /* PIN = J15 HHUSB */
800 /* PIN = H19 HSUSB */
801 /* PIN = W13, P13, R13, W16 ... */
802 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
803 __raw_writeb(0x3, base+0xde);
804 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
805 __raw_writeb(0x0, base+0x12c);
806 /* PIN = AA17->sys_clkreq mode 0 -DO- */
807 __raw_writeb(0x0, base+0x136);
808 }
809
810 } else if (btype == BOARD_H4_SDP) {
811 if (cpu == CPU_2420) {
812 /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/
813 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
814 /* Pin = Y11 VLNQ */
815 /* Pin = AA4 VLNQ */
816 /* Pin = AA6 VLNQ */
817 /* Pin = AA8 VLNQ */
818 /* Pin = AA10 VLNQ */
819 /* Pin = AA12 VLNQ */
820 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
821 __raw_writeb(0x3, base+0x10e);
822 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
823 __raw_writeb(0x3, base+0x110);
824 /* PIN = J15 MDOC_nDMAREQ */
825 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
826 __raw_writeb(0x3, base+0x114);
827 /* PIN = W13, V12, P13, R13, W19, W16 ... */
828 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
829 } else if (cpu == CPU_2422) {
830 /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */
831 /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/
832 /* Pin = Y11 VLNQ */
833 /* Pin = AA4 VLNQ */
834 /* Pin = AA6 VLNQ */
835 /* Pin = AA8 VLNQ */
836 /* Pin = AA10 VLNQ */
837 /* Pin = AA12 VLNQ */
838 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
839 __raw_writeb(0x3, base+0x10e);
840 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
841 __raw_writeb(0x3, base+0x110);
842 /* PIN = J15 MDOC_nDMAREQ */
843 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
844 __raw_writeb(0x3, base+0x114);
845 /* PIN = W13, V12, P13, R13, W19, W16 ... */
846 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
847 }
848 }
849 }
850
851 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
852 void nand_init(void)
853 {
854 extern flash_info_t flash_info[];
855
856 nand_probe(CFG_NAND_ADDR);
857 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
858 print_size(nand_dev_desc[0].totlen, "\n");
859 }
860
861 #ifdef CFG_JFFS2_MEM_NAND
862 flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
863 flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
864 flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
865 flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
866 #endif
867 }
868 #endif
"Das U-Boot" Source Tree