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git.ipfire.org Git - people/ms/u-boot.git/blob - board/omap3/evm/evm.c
2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mem.h>
34 #include <asm/arch/mux.h>
35 #include <asm/arch/sys_proto.h>
37 #include <asm/mach-types.h>
42 * Description: Early hardware init.
46 DECLARE_GLOBAL_DATA_PTR
;
48 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
49 /* board id for Linux */
50 gd
->bd
->bi_arch_number
= MACH_TYPE_OMAP3EVM
;
52 gd
->bd
->bi_boot_params
= (OMAP34XX_SDRC_CS0
+ 0x100);
58 * Routine: misc_init_r
59 * Description: Init ethernet (done here so udelay works)
64 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
65 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
68 #if defined(CONFIG_CMD_NET)
78 * Routine: set_muxconf_regs
79 * Description: Setting up the configuration Mux registers specific to the
80 * hardware. Many pins need to be moved from protect to primary
83 void set_muxconf_regs(void)
89 * Routine: setup_net_chip
90 * Description: Setting up the configuration GPMC registers specific to the
93 static void setup_net_chip(void)
95 gpio_t
*gpio3_base
= (gpio_t
*)OMAP34XX_GPIO3_BASE
;
96 gpmc_csx_t
*gpmc_cs5_base
= (gpmc_csx_t
*)GPMC_CONFIG_CS5_BASE
;
97 ctrl_t
*ctrl_base
= (ctrl_t
*)OMAP34XX_CTRL_BASE
;
99 /* Configure GPMC registers */
100 writel(NET_GPMC_CONFIG1
, &gpmc_cs5_base
->config1
);
101 writel(NET_GPMC_CONFIG2
, &gpmc_cs5_base
->config2
);
102 writel(NET_GPMC_CONFIG3
, &gpmc_cs5_base
->config3
);
103 writel(NET_GPMC_CONFIG4
, &gpmc_cs5_base
->config4
);
104 writel(NET_GPMC_CONFIG5
, &gpmc_cs5_base
->config5
);
105 writel(NET_GPMC_CONFIG6
, &gpmc_cs5_base
->config6
);
106 writel(NET_GPMC_CONFIG7
, &gpmc_cs5_base
->config7
);
108 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
109 writew(readw(&ctrl_base
->gpmc_nwe
) | 0x0E00, &ctrl_base
->gpmc_nwe
);
110 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
111 writew(readw(&ctrl_base
->gpmc_noe
) | 0x0E00, &ctrl_base
->gpmc_noe
);
112 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
113 writew(readw(&ctrl_base
->gpmc_nadv_ale
) | 0x0E00,
114 &ctrl_base
->gpmc_nadv_ale
);
116 /* Make GPIO 64 as output pin */
117 writel(readl(&gpio3_base
->oe
) & ~(GPIO0
), &gpio3_base
->oe
);
119 /* Now send a pulse on the GPIO pin */
120 writel(GPIO0
, &gpio3_base
->setdataout
);
122 writel(GPIO0
, &gpio3_base
->cleardataout
);
124 writel(GPIO0
, &gpio3_base
->setdataout
);
127 int board_eth_init(bd_t
*bis
)
130 #ifdef CONFIG_SMC911X
131 rc
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);