board/palmtreo680/palmtreo680.c

   1 /*
   2  * Palm Treo 680 Support
   3  *
   4  * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
   5  *
   6  * This file is released under the terms of GPL v2 and any later version.
   7  * See the file COPYING in the root directory of the source tree for details.
   8  *
   9  */
  10
  11 #include <common.h>
  12 #include <command.h>
  13 #include <serial.h>
  14 #include <nand.h>
  15 #include <malloc.h>
  16 #include <asm/arch/pxa-regs.h>
  17 #include <asm/arch-pxa/pxa.h>
  18 #include <asm/arch-pxa/regs-mmc.h>
  19 #include <asm/io.h>
  20 #include <asm/global_data.h>
  21 #include <u-boot/crc.h>
  22 #include <linux/mtd/docg4.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static struct nand_chip docg4_nand_chip;
  27
  28 int board_init(void)
  29 {
  30         /* We have RAM, disable cache */
  31         dcache_disable();
  32         icache_disable();
  33
  34         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  35         gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
  36
  37         return 0;
  38 }
  39
  40 int dram_init(void)
  41 {
  42         /* IPL initializes SDRAM (we're already running from it) */
  43         gd->ram_size = PHYS_SDRAM_1_SIZE;
  44         return 0;
  45 }
  46
  47 #ifdef CONFIG_LCD
  48 void lcd_enable(void)
  49 {
  50         /*
  51          * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
  52          * driver code.  We need it as an output gpio.
  53          */
  54         writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
  55
  56         /* power-up and enable the lcd */
  57         writel(0x00400000, GPSR(86)); /* enable; drive high */
  58         writel(0x00002000, GPSR(77)); /* power; drive high */
  59         writel(0x02000000, GPCR(25)); /* enable_n; drive low */
  60
  61         /* turn on LCD backlight and configure PWM for reasonable brightness */
  62         writel(0x00, PWM_CTRL0);
  63         writel(0x1b1, PWM_PERVAL0);
  64         writel(0xfd, PWM_PWDUTY0);
  65         writel(0x00000040, GPSR(38)); /*  backlight power on */
  66 }
  67 #endif
  68
  69 #ifdef CONFIG_MMC
  70 int board_mmc_init(bd_t *bis)
  71 {
  72         writel(1 << 10, GPSR(42)); /* power on */
  73         return pxa_mmc_register(0);
  74 }
  75 #endif
  76
  77 void board_nand_init(void)
  78 {
  79         /* we have one 128M diskonchip G4  */
  80
  81         struct mtd_info *mtd = &nand_info[0];
  82         struct nand_chip *nand = &docg4_nand_chip;
  83         if (docg4_nand_init(mtd, nand, 0))
  84                 hang();
  85 }
  86
  87 #ifdef CONFIG_SPL_BUILD
  88 void nand_boot(void)
  89 {
  90         __attribute__((noreturn)) void (*uboot)(void);
  91
  92         extern const void *_start, *_end;   /* boundaries of spl in memory */
  93
  94         /* size of spl; ipl loads this, and then a portion of u-boot */
  95         const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
  96
  97         /* the flash offset of the blocks that are loaded by the spl */
  98         const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
  99                 DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
 100
 101         /* total number of bytes loaded by IPL */
 102         const size_t ipl_load_size =
 103                 DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
 104
 105         /* number of bytes of u-boot proper that was loaded by the IPL */
 106         const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
 107
 108         /* number of remaining bytes of u-boot that the SPL must load */
 109         const size_t spl_load_size =
 110                 CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
 111
 112         /* memory address where we resume loading u-boot */
 113         void *const load_addr =
 114                 (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
 115
 116         /*
 117          * Copy the portion of u-boot already read from flash by the IPL to its
 118          * correct load address.
 119          */
 120         memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
 121
 122         /*
 123          * Resume loading u-boot where the IPL left off.
 124          */
 125         nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
 126
 127 #ifdef CONFIG_NAND_ENV_DST
 128         nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 129                             (void *)CONFIG_NAND_ENV_DST);
 130
 131 #ifdef CONFIG_ENV_OFFSET_REDUND
 132         nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 133                             (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 134 #endif
 135 #endif
 136         /*
 137          * Jump to U-Boot image
 138          */
 139         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 140         (*uboot)();
 141 }
 142
 143 void board_init_f(ulong bootflag)
 144 {
 145         nand_boot();
 146 }
 147
 148 #endif  /* CONFIG_SPL_BUILD */