board/pb1x00/lowlevel_init.S

   1 /* Memory sub-system initialization code */
   2
   3 #include <config.h>
   4 #include <version.h>
   5 #include <asm/regdef.h>
   6 #include <asm/au1x00.h>
   7 #include <asm/mipsregs.h>
   8
   9 #define AU1500_SYS_ADDR         0xB1900000
  10 #define sys_endian              0x0038
  11 #define CP0_Config0             $16
  12 #define MEM_1MS                 ((396000000/1000000) * 1000)
  13
  14         .text
  15         .set noreorder
  16         .set mips32
  17
  18         .globl  lowlevel_init
  19 lowlevel_init:
  20         /*
  21          * Step 1) Establish CPU endian mode.
  22          * NOTE: A fair amount of code is necessary on the Pb1000 to
  23          * obtain the value of Switch S8.1 which is used to determine
  24          * endian at run-time.
  25          */
  26
  27         /* RCE1 */
  28         li              t0, MEM_STCFG1
  29         li              t1, 0x00000083
  30         sw              t1, 0(t0)
  31
  32         li              t0, MEM_STTIME1
  33         li              t1, 0x33030A10
  34         sw              t1, 0(t0)
  35
  36         li              t0, MEM_STADDR1
  37         li              t1, 0x11803E40
  38         sw              t1, 0(t0)
  39
  40         /* Set DSTRB bits so switch will read correctly */
  41         li              t1, 0xBE00000C
  42         lw              t2, 0(t1)
  43         or              t2, t2, 0x00000300
  44         sw              t2, 0(t1)
  45
  46         /* Check switch setting */
  47         li              t1, 0xBE000014
  48         lw              t2, 0(t1)
  49         and             t2, t2, 0x00000100
  50         bne             t2, zero, big_endian
  51         nop
  52
  53 little_endian:
  54
  55         /* Change Au1 core to little endian */
  56         li      t0, AU1500_SYS_ADDR
  57         li      t1, 1
  58         sw      t1, sys_endian(t0)
  59         mfc0    t2, CP0_CONFIG
  60         mtc0    t2, CP0_CONFIG
  61         nop
  62         nop
  63
  64         /* Big Endian is default so nothing to do but fall through */
  65
  66 big_endian:
  67
  68         /*
  69          * Step 2) Establish Status Register
  70          * (set BEV, clear ERL, clear EXL, clear IE)
  71          */
  72         li      t1, 0x00400000
  73         mtc0    t1, CP0_STATUS
  74
  75         /*
  76          * Step 3) Establish CP0 Config0
  77          * (set OD, set K0=3)
  78          */
  79         li      t1, 0x00080003
  80         mtc0    t1, CP0_CONFIG
  81
  82         /*
  83          * Step 4) Disable Watchpoint facilities
  84          */
  85         li t1, 0x00000000
  86         mtc0    t1, CP0_WATCHLO
  87         mtc0    t1, CP0_IWATCHLO
  88         /*
  89          * Step 5) Disable the performance counters
  90          */
  91         mtc0    zero, CP0_PERFORMANCE
  92         nop
  93
  94         /*
  95          * Step 6) Establish EJTAG Debug register
  96          */
  97         mtc0    zero, CP0_DEBUG
  98         nop
  99
 100         /*
 101          * Step 7) Establish Cause
 102          * (set IV bit)
 103          */
 104         li      t1, 0x00800000
 105         mtc0    t1, CP0_CAUSE
 106
 107         /* Establish Wired (and Random) */
 108         mtc0    zero, CP0_WIRED
 109         nop
 110
 111         /* First setup pll:s to make serial work ok */
 112         /* We have a 12 MHz crystal */
 113         li      t0, SYS_CPUPLL
 114         li      t1, 0x21  /* 396 MHz */
 115         sw      t1, 0(t0)
 116         sync
 117         nop
 118         nop
 119
 120         /* wait 1mS for clocks to settle */
 121         li      t1, MEM_1MS
 122 1:      add     t1, -1
 123         bne     t1, zero, 1b
 124         nop
 125         /* Setup AUX PLL */
 126         li      t0, SYS_AUXPLL
 127         li      t1, 8 /* 96 MHz */
 128         sw      t1, 0(t0) /* aux pll */
 129         sync
 130
 131         /*  Static memory controller */
 132
 133         /* RCE0 8MB AMD29D323 Flash */
 134         li      t0, MEM_STCFG0
 135         li      t1, 0x00001403
 136         sw      t1, 0(t0)
 137
 138         li      t0, MEM_STTIME0
 139         li      t1, 0xFFFFFFDD
 140         sw      t1, 0(t0)
 141
 142         li      t0, MEM_STADDR0
 143         li      t1, 0x11F83FE0
 144         sw      t1, 0(t0)
 145
 146         /* RCE1 CPLD Board Logic */
 147         li      t0, MEM_STCFG1
 148         li      t1, 0x00000083
 149         sw      t1, 0(t0)
 150
 151         li      t0, MEM_STTIME1
 152         li      t1, 0x33030A10
 153         sw      t1, 0(t0)
 154
 155         li      t0, MEM_STADDR1
 156         li      t1, 0x11803E40
 157         sw      t1, 0(t0)
 158
 159         /* RCE2 CPLD Board Logic */
 160         li      t0, MEM_STCFG2
 161         li      t1, 0x00000004
 162         sw      t1, 0(t0)
 163
 164         li      t0, MEM_STTIME2
 165         li      t1, 0x08061908
 166         sw      t1, 0(t0)
 167
 168         li      t0, MEM_STADDR2
 169         li      t1, 0x12A03FC0
 170         sw      t1, 0(t0)
 171
 172         /* RCE3 PCMCIA 250ns */
 173         li      t0, MEM_STCFG3
 174         li      t1, 0x00000002
 175         sw      t1, 0(t0)
 176
 177         li      t0, MEM_STTIME3
 178         li      t1, 0x280E3E07
 179         sw      t1, 0(t0)
 180
 181         li      t0, MEM_STADDR3
 182         li      t1, 0x10000000
 183         sw      t1, 0(t0)
 184
 185         sync
 186
 187         /* Set peripherals to a known state */
 188         li      t0, IC0_CFG0CLR
 189         li      t1, 0xFFFFFFFF
 190         sw      t1, 0(t0)
 191
 192         li      t0, IC0_CFG0CLR
 193         sw      t1, 0(t0)
 194
 195         li      t0, IC0_CFG1CLR
 196         sw      t1, 0(t0)
 197
 198         li      t0, IC0_CFG2CLR
 199         sw      t1, 0(t0)
 200
 201         li      t0, IC0_SRCSET
 202         sw      t1, 0(t0)
 203
 204         li      t0, IC0_ASSIGNSET
 205         sw      t1, 0(t0)
 206
 207         li      t0, IC0_WAKECLR
 208         sw      t1, 0(t0)
 209
 210         li      t0, IC0_RISINGCLR
 211         sw      t1, 0(t0)
 212
 213         li      t0, IC0_FALLINGCLR
 214         sw      t1, 0(t0)
 215
 216         li      t0, IC0_TESTBIT
 217         li      t1, 0x00000000
 218         sw      t1, 0(t0)
 219         sync
 220
 221         li      t0, IC1_CFG0CLR
 222         li      t1, 0xFFFFFFFF
 223         sw      t1, 0(t0)
 224
 225         li      t0, IC1_CFG0CLR
 226         sw      t1, 0(t0)
 227
 228         li      t0, IC1_CFG1CLR
 229         sw      t1, 0(t0)
 230
 231         li      t0, IC1_CFG2CLR
 232         sw      t1, 0(t0)
 233
 234         li      t0, IC1_SRCSET
 235         sw      t1, 0(t0)
 236
 237         li      t0, IC1_ASSIGNSET
 238         sw      t1, 0(t0)
 239
 240         li      t0, IC1_WAKECLR
 241         sw      t1, 0(t0)
 242
 243         li      t0, IC1_RISINGCLR
 244         sw      t1, 0(t0)
 245
 246         li      t0, IC1_FALLINGCLR
 247         sw      t1, 0(t0)
 248
 249         li      t0, IC1_TESTBIT
 250         li      t1, 0x00000000
 251         sw      t1, 0(t0)
 252         sync
 253
 254         li      t0, SYS_FREQCTRL0
 255         li      t1, 0x00000000
 256         sw      t1, 0(t0)
 257
 258         li      t0, SYS_FREQCTRL1
 259         li      t1, 0x00000000
 260         sw      t1, 0(t0)
 261
 262         li      t0, SYS_CLKSRC
 263         li      t1, 0x00000000
 264         sw      t1, 0(t0)
 265
 266         li      t0, SYS_PININPUTEN
 267         li      t1, 0x00000000
 268         sw      t1, 0(t0)
 269         sync
 270
 271         li      t0, 0xB1100100
 272         li      t1, 0x00000000
 273         sw      t1, 0(t0)
 274
 275         li      t0, 0xB1400100
 276         li      t1, 0x00000000
 277         sw      t1, 0(t0)
 278
 279
 280         li      t0, SYS_WAKEMSK
 281         li      t1, 0x00000000
 282         sw      t1, 0(t0)
 283
 284         li      t0, SYS_WAKESRC
 285         li      t1, 0x00000000
 286         sw      t1, 0(t0)
 287
 288         /* wait 1mS before setup */
 289         li      t1, MEM_1MS
 290 1:      add     t1, -1
 291         bne     t1, zero, 1b
 292         nop
 293
 294         /*
 295          * Skip memory setup if we are running from memory
 296          */
 297         li              t0, 0x90000000
 298         sub             t0, ra, t0
 299         bltz            t0, skip_memsetup
 300         nop
 301
 302         /*
 303          * SDCS0 - Not used, for SMROM
 304          * SDCS1 - 32MB Micron 48LCBM16A2
 305          * SDCS2 - 32MB Micron 48LCBM16A2
 306          */
 307         li      t0, MEM_SDMODE0
 308         li      t1, 0x00000000
 309         sw      t1, 0(t0)
 310
 311         li      t0, MEM_SDMODE1
 312         li      t1, 0x00552229
 313         sw      t1, 0(t0)
 314
 315         li      t0, MEM_SDMODE2
 316         li      t1, 0x00552229
 317         sw      t1, 0(t0)
 318
 319         li      t0, MEM_SDADDR0
 320         li      t1, 0x00000000
 321         sw      t1, 0(t0)
 322
 323         li      t0, MEM_SDADDR1
 324         li      t1, 0x001003F8
 325         sw      t1, 0(t0)
 326
 327         li      t0, MEM_SDADDR2
 328         li      t1, 0x001023F8
 329         sw      t1, 0(t0)
 330
 331         sync
 332
 333         li      t0, MEM_SDREFCFG
 334         li      t1, 0x74000c30 /* Disable */
 335         sw      t1, 0(t0)
 336         sync
 337
 338         li      t0, MEM_SDPRECMD
 339         sw      zero, 0(t0)
 340         sync
 341
 342         li      t0, MEM_SDAUTOREF
 343         sw      zero, 0(t0)
 344         sync
 345         sw      zero, 0(t0)
 346         sync
 347
 348         li      t0, MEM_SDREFCFG
 349         li      t1, 0x76000c30 /* Enable */
 350         sw      t1, 0(t0)
 351         sync
 352
 353         li      t0, MEM_SDWRMD0
 354         li      t1, 0x00000023
 355         sw      t1, 0(t0)
 356         sync
 357
 358         li      t0, MEM_SDWRMD1
 359         li      t1, 0x00000023
 360         sw      t1, 0(t0)
 361         sync
 362
 363         li      t0, MEM_SDWRMD2
 364         li      t1, 0x00000023
 365         sw      t1, 0(t0)
 366         sync
 367
 368         /* wait 1mS after setup */
 369         li      t1, MEM_1MS
 370 1:      add     t1, -1
 371         bne     t1, zero, 1b
 372         nop
 373
 374 skip_memsetup:
 375
 376         li      t0, SYS_PINFUNC
 377         li      t1, 0/*0x00008080*/
 378         sw      t1, 0(t0)
 379
 380         /*
 381         li      t0, SYS_TRIOUTCLR
 382         li      t1, 0x00001FFF
 383         sw      t1, 0(t0)
 384
 385         li      t0, SYS_OUTPUTCLR
 386         li      t1, 0x00008000
 387         sw      t1, 0(t0)
 388         */
 389         sync
 390
 391         j       ra
 392         nop