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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / board / pdm360ng / pdm360ng.c
1 /*
2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
3 *
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 */
26
27 #include <common.h>
28 #include <asm/bitops.h>
29 #include <command.h>
30 #include <asm/io.h>
31 #include <asm/processor.h>
32 #include <asm/mpc512x.h>
33 #include <fdt_support.h>
34 #include <flash.h>
35 #ifdef CONFIG_MISC_INIT_R
36 #include <i2c.h>
37 #endif
38 #include <serial.h>
39 #include <jffs2/load_kernel.h>
40 #include <mtd_node.h>
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 extern flash_info_t flash_info[];
45 ulong flash_get_size (phys_addr_t base, int banknum);
46
47 /* Clocks in use */
48 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
49 CLOCK_SCCR1_LPC_EN | \
50 CLOCK_SCCR1_NFC_EN | \
51 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
52 CLOCK_SCCR1_PSCFIFO_EN | \
53 CLOCK_SCCR1_DDR_EN | \
54 CLOCK_SCCR1_FEC_EN | \
55 CLOCK_SCCR1_TPR_EN)
56
57 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
58 CLOCK_SCCR2_SPDIF_EN | \
59 CLOCK_SCCR2_DIU_EN | \
60 CLOCK_SCCR2_I2C_EN)
61
62 int board_early_init_f(void)
63 {
64 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
65
66 /*
67 * Initialize Local Window for FLASH-Bank1 access (CS1)
68 */
69 out_be32(&im->sysconf.lpcs1aw,
70 CSAW_START(CONFIG_SYS_FLASH1_BASE) |
71 CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
72 );
73 out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
74
75 /*
76 * Local Window for MRAM access (CS2)
77 */
78 out_be32(&im->sysconf.lpcs2aw,
79 CSAW_START(CONFIG_SYS_MRAM_BASE) |
80 CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
81 );
82 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
83
84 sync_law(&im->sysconf.lpcs2aw);
85
86 /*
87 * Configure Flash Speed
88 */
89 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
90 out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
91
92 /*
93 * Enable clocks
94 */
95 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
96 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
97 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
98 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
99 #endif
100
101 return 0;
102 }
103
104 sdram_conf_t mddrc_config[] = {
105 {
106 (512 << 20), /* 512 MB RAM configuration */
107 {
108 CONFIG_SYS_MDDRC_SYS_CFG,
109 CONFIG_SYS_MDDRC_TIME_CFG0,
110 CONFIG_SYS_MDDRC_TIME_CFG1,
111 CONFIG_SYS_MDDRC_TIME_CFG2
112 }
113 },
114 {
115 (128 << 20), /* 128 MB RAM configuration */
116 {
117 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
118 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
119 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
120 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
121 }
122 },
123 };
124
125 phys_size_t initdram (int board_type)
126 {
127 int i;
128 u32 msize = 0;
129 u32 pdm360ng_init_seq[] = {
130 CONFIG_SYS_DDRCMD_NOP,
131 CONFIG_SYS_DDRCMD_NOP,
132 CONFIG_SYS_DDRCMD_NOP,
133 CONFIG_SYS_DDRCMD_NOP,
134 CONFIG_SYS_DDRCMD_NOP,
135 CONFIG_SYS_DDRCMD_NOP,
136 CONFIG_SYS_DDRCMD_NOP,
137 CONFIG_SYS_DDRCMD_NOP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_PCHG_ALL,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_RFSH,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_RFSH,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_MICRON_INIT_DEV_OP,
147 CONFIG_SYS_DDRCMD_NOP,
148 CONFIG_SYS_DDRCMD_EM2,
149 CONFIG_SYS_DDRCMD_NOP,
150 CONFIG_SYS_DDRCMD_PCHG_ALL,
151 CONFIG_SYS_DDRCMD_EM2,
152 CONFIG_SYS_DDRCMD_EM3,
153 CONFIG_SYS_DDRCMD_EN_DLL,
154 CONFIG_SYS_DDRCMD_RES_DLL,
155 CONFIG_SYS_DDRCMD_PCHG_ALL,
156 CONFIG_SYS_DDRCMD_RFSH,
157 CONFIG_SYS_DDRCMD_RFSH,
158 CONFIG_SYS_MICRON_INIT_DEV_OP,
159 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
160 CONFIG_SYS_DDRCMD_OCD_EXIT,
161 CONFIG_SYS_DDRCMD_PCHG_ALL,
162 CONFIG_SYS_DDRCMD_NOP
163 };
164
165 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
166 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
167 ARRAY_SIZE(pdm360ng_init_seq));
168 if (msize == mddrc_config[i].size)
169 break;
170 }
171
172 return msize;
173 }
174
175 #if defined(CONFIG_SERIAL_MULTI)
176 static int set_lcd_brightness(char *);
177 #endif
178
179 int misc_init_r(void)
180 {
181 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
182
183 /*
184 * Re-configure flash setup using auto-detected info
185 */
186 if (flash_info[1].size > 0) {
187 out_be32(&im->sysconf.lpcs1aw,
188 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
189 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
190 flash_info[1].size));
191 sync_law(&im->sysconf.lpcs1aw);
192 /*
193 * Re-check to get correct base address
194 */
195 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
196 } else {
197 /* Disable Bank 1 */
198 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
199 sync_law(&im->sysconf.lpcs1aw);
200 }
201
202 out_be32(&im->sysconf.lpcs0aw,
203 CSAW_START(gd->bd->bi_flashstart) |
204 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
205 sync_law(&im->sysconf.lpcs0aw);
206
207 /*
208 * Re-check to get correct base address
209 */
210 flash_get_size (gd->bd->bi_flashstart, 0);
211
212 /*
213 * Re-do flash protection upon new addresses
214 */
215 flash_protect (FLAG_PROTECT_CLEAR,
216 gd->bd->bi_flashstart, 0xffffffff,
217 &flash_info[0]);
218
219 /* Monitor protection ON by default */
220 flash_protect (FLAG_PROTECT_SET,
221 CONFIG_SYS_MONITOR_BASE,
222 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
223 &flash_info[0]);
224
225 /* Environment protection ON by default */
226 flash_protect (FLAG_PROTECT_SET,
227 CONFIG_ENV_ADDR,
228 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
229 &flash_info[0]);
230
231 #ifdef CONFIG_ENV_ADDR_REDUND
232 /* Redundant environment protection ON by default */
233 flash_protect (FLAG_PROTECT_SET,
234 CONFIG_ENV_ADDR_REDUND,
235 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
236 &flash_info[0]);
237 #endif
238
239 #ifdef CONFIG_FSL_DIU_FB
240 #if defined(CONFIG_SERIAL_MULTI)
241 set_lcd_brightness(0);
242 #endif
243 /* Switch LCD-Backlight and LVDS-Interface on */
244 setbits_be32(&im->gpio.gpdir, 0x01040000);
245 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
246 #endif
247
248 #if defined(CONFIG_HARD_I2C)
249 if (!getenv("ethaddr")) {
250 uchar buf[6];
251 uchar ifm_oui[3] = { 0, 2, 1, };
252 int ret;
253
254 /* I2C-0 for on-board eeprom */
255 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
256
257 /* Read ethaddr from EEPROM */
258 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
259 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
260 if (ret != 0) {
261 printf("Error: Unable to read MAC from I2C"
262 " EEPROM at address %02X:%02X\n",
263 CONFIG_SYS_I2C_EEPROM_ADDR,
264 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
265 return 1;
266 }
267
268 /* Owned by IFM ? */
269 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
270 printf("Illegal MAC address in EEPROM: %pM\n", buf);
271 return 1;
272 }
273
274 eth_setenv_enetaddr("ethaddr", buf);
275 }
276 #endif /* defined(CONFIG_HARD_I2C) */
277
278 return 0;
279 }
280
281 static iopin_t ioregs_init[] = {
282 /* FUNC1=LPC_CS4 */
283 {
284 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
285 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
286 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
287 },
288 /* FUNC3=GPIO10 */
289 {
290 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
291 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
292 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
293 },
294 /* FUNC1=CAN3_TX */
295 {
296 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
297 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
298 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
299 },
300 /* FUNC3=GPIO14 */
301 {
302 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
303 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
304 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
305 },
306 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
307 /* DIU_LD22-DIU_LD23 */
308 {
309 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
310 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
311 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
312 },
313 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
314 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
315 {
316 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
317 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
318 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
319 },
320 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
321 /* VIU_DATA0-VIU_DATA2 */
322 {
323 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
324 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
325 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
326 },
327 /* FUNC2=FEC_TXD_0 */
328 {
329 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
330 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
331 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
332 },
333 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
334 /* VIU_DATA3, VIU_DATA4 */
335 {
336 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
337 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
338 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
339 },
340 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
341 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
342 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
343 {
344 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
345 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
346 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
347 },
348 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
349 /* DIU_LD00-DIU_LD21 */
350 {
351 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
352 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
353 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
354 },
355 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
356 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
357 {
358 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
359 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
360 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
361 },
362 /* FUNC2=CAN3_RX */
363 {
364 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
365 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
366 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
367 },
368 /* Sets lowest slew on 2 CAN_TX Pins*/
369 {
370 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
371 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
372 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
373 },
374 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
375 /* CAN4_TX, CAN4_RX */
376 {
377 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
378 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
379 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
380 },
381 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
382 /* GPIO8, GPIO9 */
383 {
384 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
385 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
386 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
387 },
388 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
389 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
390 {
391 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
392 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
393 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
394 },
395 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
396 /* FEC_RXD_3, FEC_RXD_2 */
397 {
398 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
399 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
400 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
401 },
402 /* FUNC3=GPIO17 */
403 {
404 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
405 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
406 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
407 },
408 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
409 /* GPIO2, GPIO20, GPIO21 */
410 {
411 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
412 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
413 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
414 },
415 /* FUNC2=VIU_PIX_CLK */
416 {
417 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
418 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
419 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
420 },
421 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
422 /* GPIO24, GPIO25 */
423 {
424 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
425 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
426 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
427 },
428 /* FUNC1=NFC_CE2 */
429 {
430 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
431 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
432 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
433 },
434 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
435 /* VIU_DATA5-VIU_DATA9 */
436 {
437 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
438 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
439 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
440 },
441 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
442 /* LPC_TSIZ1-LPC_TSIZ2 */
443 {
444 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
445 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
446 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
447 },
448 /* FUNC1=LPC_TS */
449 {
450 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
451 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
452 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
453 },
454 /* FUNC3=GPIO16 */
455 {
456 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
457 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
458 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
459 },
460 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
461 /* GPIO18-GPIO19, GPT7/GPIO7 */
462 {
463 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
464 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
465 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
466 },
467 /* FUNC3=GPIO0/GPT0 */
468 {
469 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
470 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
471 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
472 },
473 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
474 /* GPIO11, GPIO2, GPIO12, GPIO13 */
475 {
476 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
477 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
478 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
479 },
480 /* FUNC2=DIU_DE */
481 {
482 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
483 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
484 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
485 }
486 };
487
488 int checkboard (void)
489 {
490 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
491
492 puts("Board: PDM360NG\n");
493
494 /* initialize function mux & slew rate IO inter alia on IO Pins */
495
496 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
497
498 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
499 setbits_be32(&im->io_ctrl.io_control_gp,
500 (1 << 0) | /* GP_MUX7->GPIO7 */
501 (1 << 5)); /* GP_MUX2->GPIO2 */
502
503 /* configure GPIO24 (VIU_CE), output/high */
504 setbits_be32(&im->gpio.gpdir, 0x80);
505 setbits_be32(&im->gpio.gpdat, 0x80);
506
507 return 0;
508 }
509
510 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
511 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
512 struct node_info nodes[] = {
513 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
514 { "cfi-flash", MTD_DEV_TYPE_NOR, },
515 };
516 #endif
517
518 #if defined(CONFIG_VIDEO)
519 /*
520 * EDID block has been generated using Phoenix EDID Designer 1.3.
521 * This tool creates a text file containing:
522 *
523 * EDID BYTES:
524 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
525 * ------------------------------------------------
526 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
527 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
528 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
529 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
530 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
531 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
532 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
533 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
534 *
535 * Then this data has been manually converted to the char
536 * array below.
537 */
538 static unsigned char edid_buf[128] = {
539 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
540 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
541 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
542 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
543 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
544 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
545 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
546 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
547 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
548 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
549 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
550 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
551 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
552 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
553 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
554 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
555 };
556 #endif
557
558 void ft_board_setup(void *blob, bd_t *bd)
559 {
560 u32 val[8];
561 int rc, i = 0;
562
563 ft_cpu_setup(blob, bd);
564 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
565 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
566 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
567 #endif
568 #if defined(CONFIG_VIDEO)
569 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
570 #endif
571
572 /* Fixup NOR FLASH mapping */
573 val[i++] = 0; /* chip select number */
574 val[i++] = 0; /* always 0 */
575 val[i++] = gd->bd->bi_flashstart;
576 val[i++] = gd->bd->bi_flashsize;
577
578 /* Fixup MRAM mapping */
579 val[i++] = 2; /* chip select number */
580 val[i++] = 0; /* always 0 */
581 val[i++] = CONFIG_SYS_MRAM_BASE;
582 val[i++] = CONFIG_SYS_MRAM_SIZE;
583
584 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
585 val, i * sizeof(u32), 1);
586 if (rc)
587 printf("Unable to update localbus ranges, err=%s\n",
588 fdt_strerror(rc));
589
590 /* Fixup reg property in NOR Flash node */
591 i = 0;
592 val[i++] = 0; /* always 0 */
593 val[i++] = 0; /* start at offset 0 */
594 val[i++] = flash_info[0].size; /* size of Bank 0 */
595
596 /* Second Bank available? */
597 if (flash_info[1].size > 0) {
598 val[i++] = 0; /* always 0 */
599 val[i++] = flash_info[0].size; /* offset of Bank 1 */
600 val[i++] = flash_info[1].size; /* size of Bank 1 */
601 }
602
603 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
604 val, i * sizeof(u32), 1);
605 if (rc)
606 printf("Unable to update flash reg property, err=%s\n",
607 fdt_strerror(rc));
608 }
609 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
610
611 #if defined(CONFIG_SERIAL_MULTI)
612 /*
613 * If argument is NULL, set the LCD brightness to the
614 * value from "brightness" environment variable. Set
615 * the LCD brightness to the value specified by the
616 * argument otherwise. Default brightness is zero.
617 */
618 #define MAX_BRIGHTNESS 99
619 static int set_lcd_brightness(char *brightness)
620 {
621 struct stdio_dev *cop_port;
622 char *env;
623 char cmd_buf[20];
624 int val = 0;
625 int cs = 0;
626 int len, i;
627
628 if (brightness) {
629 val = simple_strtol(brightness, NULL, 10);
630 } else {
631 env = getenv("brightness");
632 if (env)
633 val = simple_strtol(env, NULL, 10);
634 }
635
636 if (val < 0)
637 val = 0;
638
639 if (val > MAX_BRIGHTNESS)
640 val = MAX_BRIGHTNESS;
641
642 sprintf(cmd_buf, "$SB;%04d;", val);
643
644 len = strlen(cmd_buf);
645 for (i = 1; i <= len; i++)
646 cs += cmd_buf[i];
647
648 cs = (~cs + 1) & 0xff;
649 sprintf(cmd_buf + len, "%02X\n", cs);
650
651 /* IO Coprocessor communication */
652 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
653 if (!cop_port) {
654 printf("Error: Can't open IO Coprocessor port.\n");
655 return -1;
656 }
657
658 debug("%s: cmd: %s", __func__, cmd_buf);
659 write_port(cop_port, cmd_buf);
660 /*
661 * Wait for transmission and maybe response data
662 * before closing the port.
663 */
664 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
665 memset(cmd_buf, 0, sizeof(cmd_buf));
666 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
667 if (len)
668 printf("Error: %s\n", cmd_buf);
669
670 close_port(4);
671
672 return 0;
673 }
674
675 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
676 int argc, char * const argv[])
677 {
678 if (argc < 2)
679 return cmd_usage(cmdtp);
680
681 return set_lcd_brightness(argv[1]);
682 }
683
684 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
685 "set LCD brightness",
686 "<brightness> - set LCD backlight level to <brightness>.\n"
687 );
688 #endif /* CONFIG_SERIAL_MULTI */
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