1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
7 * Copyright (C) 2013 Lemonage Software GmbH
8 * Author Lars Poeschel <poeschel@lemonage.de>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 /* MII mode defines */
34 #define RMII_RGMII2_MODE_ENABLE 0x49
36 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
38 #ifdef CONFIG_SPL_BUILD
41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
43 #define OSC (V_OSCK/1000000)
44 const struct dpll_params dpll_ddr
= {
45 DDR_CLK_MHZ
, OSC
-1, 1, -1, -1, -1, -1};
47 const struct dpll_params
*get_dpll_ddr_params(void)
53 const struct ctrl_ioregs ioregs
= {
54 .cm0ioctl
= MT41J256M8HX15E_IOCTRL_VALUE
,
55 .cm1ioctl
= MT41J256M8HX15E_IOCTRL_VALUE
,
56 .cm2ioctl
= MT41J256M8HX15E_IOCTRL_VALUE
,
57 .dt0ioctl
= MT41J256M8HX15E_IOCTRL_VALUE
,
58 .dt1ioctl
= MT41J256M8HX15E_IOCTRL_VALUE
,
61 static const struct ddr_data ddr3_data
= {
62 .datardsratio0
= MT41J256M8HX15E_RD_DQS
,
63 .datawdsratio0
= MT41J256M8HX15E_WR_DQS
,
64 .datafwsratio0
= MT41J256M8HX15E_PHY_FIFO_WE
,
65 .datawrsratio0
= MT41J256M8HX15E_PHY_WR_DATA
,
68 static const struct cmd_control ddr3_cmd_ctrl_data
= {
69 .cmd0csratio
= MT41J256M8HX15E_RATIO
,
70 .cmd0iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
72 .cmd1csratio
= MT41J256M8HX15E_RATIO
,
73 .cmd1iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
75 .cmd2csratio
= MT41J256M8HX15E_RATIO
,
76 .cmd2iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
79 static struct emif_regs ddr3_emif_reg_data
= {
80 .sdram_config
= MT41J256M8HX15E_EMIF_SDCFG
,
81 .ref_ctrl
= MT41J256M8HX15E_EMIF_SDREF
,
82 .sdram_tim1
= MT41J256M8HX15E_EMIF_TIM1
,
83 .sdram_tim2
= MT41J256M8HX15E_EMIF_TIM2
,
84 .sdram_tim3
= MT41J256M8HX15E_EMIF_TIM3
,
85 .zq_config
= MT41J256M8HX15E_ZQ_CFG
,
86 .emif_ddr_phy_ctlr_1
= MT41J256M8HX15E_EMIF_READ_LATENCY
|
92 config_ddr(DDR_CLK_MHZ
, &ioregs
, &ddr3_data
,
93 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
96 const struct ctrl_ioregs ioregs
= {
97 .cm0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
98 .cm1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
99 .cm2ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
100 .dt0ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
101 .dt1ioctl
= MT41K256M16HA125E_IOCTRL_VALUE
,
104 static const struct ddr_data ddr3_data
= {
105 .datardsratio0
= MT41K256M16HA125E_RD_DQS
,
106 .datawdsratio0
= MT41K256M16HA125E_WR_DQS
,
107 .datafwsratio0
= MT41K256M16HA125E_PHY_FIFO_WE
,
108 .datawrsratio0
= MT41K256M16HA125E_PHY_WR_DATA
,
111 static const struct cmd_control ddr3_cmd_ctrl_data
= {
112 .cmd0csratio
= MT41K256M16HA125E_RATIO
,
113 .cmd0iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
115 .cmd1csratio
= MT41K256M16HA125E_RATIO
,
116 .cmd1iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
118 .cmd2csratio
= MT41K256M16HA125E_RATIO
,
119 .cmd2iclkout
= MT41K256M16HA125E_INVERT_CLKOUT
,
122 static struct emif_regs ddr3_emif_reg_data
= {
123 .sdram_config
= MT41K256M16HA125E_EMIF_SDCFG
,
124 .ref_ctrl
= MT41K256M16HA125E_EMIF_SDREF
,
125 .sdram_tim1
= MT41K256M16HA125E_EMIF_TIM1
,
126 .sdram_tim2
= MT41K256M16HA125E_EMIF_TIM2
,
127 .sdram_tim3
= MT41K256M16HA125E_EMIF_TIM3
,
128 .zq_config
= MT41K256M16HA125E_ZQ_CFG
,
129 .emif_ddr_phy_ctlr_1
= MT41K256M16HA125E_EMIF_READ_LATENCY
|
133 void sdram_init(void)
135 config_ddr(DDR_CLK_MHZ
, &ioregs
, &ddr3_data
,
136 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
140 void set_uart_mux_conf(void)
142 enable_uart0_pin_mux();
145 void set_mux_conf_regs(void)
147 /* Initalize the board header */
148 enable_i2c0_pin_mux();
149 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
151 enable_board_pin_mux();
156 * Basic board specific setup. Pinmux has been handled already.
160 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
162 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
167 #ifdef CONFIG_DRIVER_TI_CPSW
168 static void cpsw_control(int enabled
)
170 /* VTP can be added here */
175 static struct cpsw_slave_data cpsw_slaves
[] = {
177 .slave_reg_ofs
= 0x208,
178 .sliver_reg_ofs
= 0xd80,
180 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
183 .slave_reg_ofs
= 0x308,
184 .sliver_reg_ofs
= 0xdc0,
186 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
190 static struct cpsw_platform_data cpsw_data
= {
191 .mdio_base
= CPSW_MDIO_BASE
,
192 .cpsw_base
= CPSW_BASE
,
195 .cpdma_reg_ofs
= 0x800,
197 .slave_data
= cpsw_slaves
,
198 .ale_reg_ofs
= 0xd00,
200 .host_port_reg_ofs
= 0x108,
201 .hw_stats_reg_ofs
= 0x900,
202 .bd_ram_ofs
= 0x2000,
203 .mac_control
= (1 << 5),
204 .control
= cpsw_control
,
206 .version
= CPSW_CTRL_VERSION_2
,
210 #if defined(CONFIG_DRIVER_TI_CPSW) || \
211 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
212 int board_eth_init(bd_t
*bis
)
215 #ifdef CONFIG_DRIVER_TI_CPSW
217 uint32_t mac_hi
, mac_lo
;
219 if (!eth_env_get_enetaddr("ethaddr", mac_addr
)) {
220 printf("<ethaddr> not set. Reading from E-fuse\n");
221 /* try reading mac address from efuse */
222 mac_lo
= readl(&cdev
->macid0l
);
223 mac_hi
= readl(&cdev
->macid0h
);
224 mac_addr
[0] = mac_hi
& 0xFF;
225 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
226 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
227 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
228 mac_addr
[4] = mac_lo
& 0xFF;
229 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
231 if (is_valid_ethaddr(mac_addr
))
232 eth_env_set_enetaddr("ethaddr", mac_addr
);
237 writel(RMII_RGMII2_MODE_ENABLE
, &cdev
->miisel
);
239 rv
= cpsw_register(&cpsw_data
);
241 printf("Error %d registering CPSW switch\n", rv
);
247 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
248 rv
= usb_eth_initialize(bis
);
250 printf("Error %d registering USB_ETHER\n", rv
);