4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 /* MII mode defines */
34 #define RMII_RGMII2_MODE_ENABLE 0x49
36 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
38 #ifdef CONFIG_SPL_BUILD
41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
43 #define OSC (V_OSCK/1000000)
44 const struct dpll_params dpll_ddr
= {
45 DDR_CLK_MHZ
, OSC
-1, 1, -1, -1, -1, -1};
47 const struct dpll_params
*get_dpll_ddr_params(void)
52 static const struct ddr_data ddr3_data
= {
53 .datardsratio0
= MT41J256M8HX15E_RD_DQS
,
54 .datawdsratio0
= MT41J256M8HX15E_WR_DQS
,
55 .datafwsratio0
= MT41J256M8HX15E_PHY_FIFO_WE
,
56 .datawrsratio0
= MT41J256M8HX15E_PHY_WR_DATA
,
57 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
60 static const struct cmd_control ddr3_cmd_ctrl_data
= {
61 .cmd0csratio
= MT41J256M8HX15E_RATIO
,
62 .cmd0dldiff
= MT41J256M8HX15E_DLL_LOCK_DIFF
,
63 .cmd0iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
65 .cmd1csratio
= MT41J256M8HX15E_RATIO
,
66 .cmd1dldiff
= MT41J256M8HX15E_DLL_LOCK_DIFF
,
67 .cmd1iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
69 .cmd2csratio
= MT41J256M8HX15E_RATIO
,
70 .cmd2dldiff
= MT41J256M8HX15E_DLL_LOCK_DIFF
,
71 .cmd2iclkout
= MT41J256M8HX15E_INVERT_CLKOUT
,
74 static struct emif_regs ddr3_emif_reg_data
= {
75 .sdram_config
= MT41J256M8HX15E_EMIF_SDCFG
,
76 .ref_ctrl
= MT41J256M8HX15E_EMIF_SDREF
,
77 .sdram_tim1
= MT41J256M8HX15E_EMIF_TIM1
,
78 .sdram_tim2
= MT41J256M8HX15E_EMIF_TIM2
,
79 .sdram_tim3
= MT41J256M8HX15E_EMIF_TIM3
,
80 .zq_config
= MT41J256M8HX15E_ZQ_CFG
,
81 .emif_ddr_phy_ctlr_1
= MT41J256M8HX15E_EMIF_READ_LATENCY
|
85 void set_uart_mux_conf(void)
87 enable_uart0_pin_mux();
90 void set_mux_conf_regs(void)
92 /* Initalize the board header */
93 enable_i2c0_pin_mux();
94 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
96 enable_board_pin_mux();
101 config_ddr(DDR_CLK_MHZ
, MT41J256M8HX15E_IOCTRL_VALUE
, &ddr3_data
,
102 &ddr3_cmd_ctrl_data
, &ddr3_emif_reg_data
, 0);
107 * Basic board specific setup. Pinmux has been handled already.
111 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
113 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
118 #ifdef CONFIG_DRIVER_TI_CPSW
119 static void cpsw_control(int enabled
)
121 /* VTP can be added here */
126 static struct cpsw_slave_data cpsw_slaves
[] = {
128 .slave_reg_ofs
= 0x208,
129 .sliver_reg_ofs
= 0xd80,
131 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
134 .slave_reg_ofs
= 0x308,
135 .sliver_reg_ofs
= 0xdc0,
137 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
141 static struct cpsw_platform_data cpsw_data
= {
142 .mdio_base
= CPSW_MDIO_BASE
,
143 .cpsw_base
= CPSW_BASE
,
146 .cpdma_reg_ofs
= 0x800,
148 .slave_data
= cpsw_slaves
,
149 .ale_reg_ofs
= 0xd00,
151 .host_port_reg_ofs
= 0x108,
152 .hw_stats_reg_ofs
= 0x900,
153 .bd_ram_ofs
= 0x2000,
154 .mac_control
= (1 << 5),
155 .control
= cpsw_control
,
157 .version
= CPSW_CTRL_VERSION_2
,
161 #if defined(CONFIG_DRIVER_TI_CPSW) || \
162 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
163 int board_eth_init(bd_t
*bis
)
166 #ifdef CONFIG_DRIVER_TI_CPSW
168 uint32_t mac_hi
, mac_lo
;
170 if (!eth_getenv_enetaddr("ethaddr", mac_addr
)) {
171 printf("<ethaddr> not set. Reading from E-fuse\n");
172 /* try reading mac address from efuse */
173 mac_lo
= readl(&cdev
->macid0l
);
174 mac_hi
= readl(&cdev
->macid0h
);
175 mac_addr
[0] = mac_hi
& 0xFF;
176 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
177 mac_addr
[2] = (mac_hi
& 0xFF0000) >> 16;
178 mac_addr
[3] = (mac_hi
& 0xFF000000) >> 24;
179 mac_addr
[4] = mac_lo
& 0xFF;
180 mac_addr
[5] = (mac_lo
& 0xFF00) >> 8;
182 if (is_valid_ether_addr(mac_addr
))
183 eth_setenv_enetaddr("ethaddr", mac_addr
);
188 writel(RMII_RGMII2_MODE_ENABLE
, &cdev
->miisel
);
190 rv
= cpsw_register(&cpsw_data
);
192 printf("Error %d registering CPSW switch\n", rv
);
198 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
199 rv
= usb_eth_initialize(bis
);
201 printf("Error %d registering USB_ETHER\n", rv
);