board/phytec/pcm051/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
   5  *
   6  * Copyright (C) 2013 Lemonage Software GmbH
   7  * Author Lars Poeschel <poeschel@lemonage.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <environment.h>
  14 #include <errno.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <cpsw.h>
  30 #include "board.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* MII mode defines */
  35 #define RMII_RGMII2_MODE_ENABLE 0x49
  36
  37 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  38
  39 #ifdef CONFIG_SPL_BUILD
  40
  41 /* DDR RAM defines */
  42 #define DDR_CLK_MHZ             303 /* DDR_DPLL_MULT value */
  43
  44 #define OSC     (V_OSCK/1000000)
  45 const struct dpll_params dpll_ddr = {
  46                 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
  47
  48 const struct dpll_params *get_dpll_ddr_params(void)
  49 {
  50         return &dpll_ddr;
  51 }
  52
  53 #ifdef CONFIG_REV1
  54 const struct ctrl_ioregs ioregs = {
  55         .cm0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  56         .cm1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  57         .cm2ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  58         .dt0ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  59         .dt1ioctl               = MT41J256M8HX15E_IOCTRL_VALUE,
  60 };
  61
  62 static const struct ddr_data ddr3_data = {
  63         .datardsratio0 = MT41J256M8HX15E_RD_DQS,
  64         .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  65         .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
  66         .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
  67 };
  68
  69 static const struct cmd_control ddr3_cmd_ctrl_data = {
  70         .cmd0csratio = MT41J256M8HX15E_RATIO,
  71         .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  72
  73         .cmd1csratio = MT41J256M8HX15E_RATIO,
  74         .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  75
  76         .cmd2csratio = MT41J256M8HX15E_RATIO,
  77         .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  78 };
  79
  80 static struct emif_regs ddr3_emif_reg_data = {
  81         .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
  82         .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
  83         .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
  84         .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
  85         .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
  86         .zq_config = MT41J256M8HX15E_ZQ_CFG,
  87         .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
  88                                 PHY_EN_DYN_PWRDN,
  89 };
  90
  91 void sdram_init(void)
  92 {
  93         config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  94                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  95 }
  96 #else
  97 const struct ctrl_ioregs ioregs = {
  98         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
  99         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 100         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 101         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 102         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 103 };
 104
 105 static const struct ddr_data ddr3_data = {
 106         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 107         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 108         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 109         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 110 };
 111
 112 static const struct cmd_control ddr3_cmd_ctrl_data = {
 113         .cmd0csratio = MT41K256M16HA125E_RATIO,
 114         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 115
 116         .cmd1csratio = MT41K256M16HA125E_RATIO,
 117         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 118
 119         .cmd2csratio = MT41K256M16HA125E_RATIO,
 120         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 121 };
 122
 123 static struct emif_regs ddr3_emif_reg_data = {
 124         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 125         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 126         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 127         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 128         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 129         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 130         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
 131                                 PHY_EN_DYN_PWRDN,
 132 };
 133
 134 void sdram_init(void)
 135 {
 136         config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
 137                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 138 }
 139 #endif
 140
 141 void set_uart_mux_conf(void)
 142 {
 143         enable_uart0_pin_mux();
 144 }
 145
 146 void set_mux_conf_regs(void)
 147 {
 148         /* Initalize the board header */
 149         enable_i2c0_pin_mux();
 150         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 151
 152         enable_board_pin_mux();
 153 }
 154 #endif
 155
 156 /*
 157  * Basic board specific setup.  Pinmux has been handled already.
 158  */
 159 int board_init(void)
 160 {
 161         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 162
 163         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 164
 165         return 0;
 166 }
 167
 168 #ifdef CONFIG_DRIVER_TI_CPSW
 169 static void cpsw_control(int enabled)
 170 {
 171         /* VTP can be added here */
 172
 173         return;
 174 }
 175
 176 static struct cpsw_slave_data cpsw_slaves[] = {
 177         {
 178                 .slave_reg_ofs  = 0x208,
 179                 .sliver_reg_ofs = 0xd80,
 180                 .phy_addr       = 0,
 181                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 182         },
 183         {
 184                 .slave_reg_ofs  = 0x308,
 185                 .sliver_reg_ofs = 0xdc0,
 186                 .phy_addr       = 1,
 187                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
 188         },
 189 };
 190
 191 static struct cpsw_platform_data cpsw_data = {
 192         .mdio_base              = CPSW_MDIO_BASE,
 193         .cpsw_base              = CPSW_BASE,
 194         .mdio_div               = 0xff,
 195         .channels               = 8,
 196         .cpdma_reg_ofs          = 0x800,
 197         .slaves                 = 1,
 198         .slave_data             = cpsw_slaves,
 199         .ale_reg_ofs            = 0xd00,
 200         .ale_entries            = 1024,
 201         .host_port_reg_ofs      = 0x108,
 202         .hw_stats_reg_ofs       = 0x900,
 203         .bd_ram_ofs             = 0x2000,
 204         .mac_control            = (1 << 5),
 205         .control                = cpsw_control,
 206         .host_port_num          = 0,
 207         .version                = CPSW_CTRL_VERSION_2,
 208 };
 209 #endif
 210
 211 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 212         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 213 int board_eth_init(bd_t *bis)
 214 {
 215         int rv, n = 0;
 216 #ifdef CONFIG_DRIVER_TI_CPSW
 217         uint8_t mac_addr[6];
 218         uint32_t mac_hi, mac_lo;
 219
 220         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
 221                 printf("<ethaddr> not set. Reading from E-fuse\n");
 222                 /* try reading mac address from efuse */
 223                 mac_lo = readl(&cdev->macid0l);
 224                 mac_hi = readl(&cdev->macid0h);
 225                 mac_addr[0] = mac_hi & 0xFF;
 226                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 227                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 228                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 229                 mac_addr[4] = mac_lo & 0xFF;
 230                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 231
 232                 if (is_valid_ethaddr(mac_addr))
 233                         eth_env_set_enetaddr("ethaddr", mac_addr);
 234                 else
 235                         goto try_usbether;
 236         }
 237
 238         writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
 239
 240         rv = cpsw_register(&cpsw_data);
 241         if (rv < 0)
 242                 printf("Error %d registering CPSW switch\n", rv);
 243         else
 244                 n += rv;
 245 try_usbether:
 246 #endif
 247
 248 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
 249         rv = usb_eth_initialize(bis);
 250         if (rv < 0)
 251                 printf("Error %d registering USB_ETHER\n", rv);
 252         else
 253                 n += rv;
 254 #endif
 255         return n;
 256 }
 257 #endif