2 * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <asm/mach-imx/spi.h>
19 #include <linux/errno.h>
23 #include <fsl_esdhc.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/sections.h>
30 DECLARE_GLOBAL_DATA_PTR
;
32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
34 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
48 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
52 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
55 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
58 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
59 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
60 #define GREEN_LED IMX_GPIO_NR(2, 31)
61 #define RED_LED IMX_GPIO_NR(1, 30)
62 #define IMX6Q_DRIVE_STRENGTH 0x30
66 gd
->ram_size
= imx_ddr_size();
70 static iomux_v3_cfg_t
const uart4_pads
[] = {
71 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
72 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
75 static iomux_v3_cfg_t
const enet_pads
[] = {
76 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
77 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
78 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
79 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
80 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
81 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
82 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
83 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
84 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
85 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
|
86 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
87 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
88 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
89 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
90 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
91 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
92 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
93 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
94 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
97 static iomux_v3_cfg_t
const ecspi3_pads
[] = {
98 IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
99 IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
100 IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO
| MUX_PAD_CTRL(SPI_PAD_CTRL
)),
101 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
104 static iomux_v3_cfg_t
const gpios_pads
[] = {
105 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
106 IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
107 IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
108 IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
109 IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
110 IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
111 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
112 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
115 #ifdef CONFIG_CMD_NAND
117 static iomux_v3_cfg_t
const nfc_pads
[] = {
118 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
119 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
120 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
121 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
122 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
123 IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
124 IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
125 IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
126 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
127 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
128 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
129 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
130 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
131 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
132 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
133 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
134 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
135 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
136 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS
| MUX_PAD_CTRL(NAND_PAD_CTRL
)),
140 static struct i2c_pads_info i2c_pad_info
= {
142 .i2c_mode
= MX6Q_PAD_EIM_D21__I2C1_SCL
| I2C_PAD
,
143 .gpio_mode
= MX6Q_PAD_EIM_D21__GPIO3_IO21
| I2C_PAD
,
144 .gp
= IMX_GPIO_NR(3, 21)
147 .i2c_mode
= MX6Q_PAD_EIM_D28__I2C1_SDA
| I2C_PAD
,
148 .gpio_mode
= MX6Q_PAD_EIM_D28__GPIO3_IO28
| I2C_PAD
,
149 .gp
= IMX_GPIO_NR(3, 28)
153 static struct fsl_esdhc_cfg usdhc_cfg
[] = {
156 {.esdhc_base
= USDHC2_BASE_ADDR
,
160 #if !defined(CONFIG_SPL_BUILD)
161 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
162 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
163 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
164 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
165 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
166 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
167 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
168 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
169 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
173 static iomux_v3_cfg_t
const usdhc3_pads
[] = {
174 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
175 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
176 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
177 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
178 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
179 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
180 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
181 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
182 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
183 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
186 int board_mmc_get_env_dev(int devno
)
191 int board_mmc_getcd(struct mmc
*mmc
)
193 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
196 switch (cfg
->esdhc_base
) {
197 case USDHC2_BASE_ADDR
:
198 ret
= !gpio_get_value(USDHC2_CD_GPIO
);
201 case USDHC3_BASE_ADDR
:
209 #ifndef CONFIG_SPL_BUILD
210 int board_mmc_init(bd_t
*bis
)
215 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
218 SETUP_IOMUX_PADS(usdhc3_pads
);
219 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
222 SETUP_IOMUX_PADS(usdhc2_pads
);
223 gpio_direction_input(USDHC2_CD_GPIO
);
224 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
227 printf("Warning: you configured more USDHC controllers"
228 "(%d) then supported by the board (%d)\n",
229 i
+ 1, CONFIG_SYS_FSL_USDHC_NUM
);
233 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
242 static void setup_iomux_uart(void)
244 SETUP_IOMUX_PADS(uart4_pads
);
247 static void setup_iomux_enet(void)
249 SETUP_IOMUX_PADS(enet_pads
);
251 gpio_direction_output(ENET_PHY_RESET_GPIO
, 0);
253 gpio_set_value(ENET_PHY_RESET_GPIO
, 1);
257 static void setup_spi(void)
259 gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
260 gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
262 SETUP_IOMUX_PADS(ecspi3_pads
);
264 enable_spi_clk(true, 2);
267 static void setup_gpios(void)
269 SETUP_IOMUX_PADS(gpios_pads
);
272 #ifdef CONFIG_CMD_NAND
273 static void setup_gpmi_nand(void)
275 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
277 /* config gpmi nand iomux */
278 SETUP_IOMUX_PADS(nfc_pads
);
280 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
281 clrbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
283 /* config gpmi and bch clock to 100 MHz */
284 clrsetbits_le32(&mxc_ccm
->cs2cdr
,
285 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
286 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
287 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
288 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
289 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
290 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
292 /* enable ENFC_CLK_ROOT clock */
293 setbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
295 /* enable gpmi and bch clock gating */
296 setbits_le32(&mxc_ccm
->CCGR4
,
297 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
298 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
299 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
300 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
301 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET
);
303 /* enable apbh clock gating */
304 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
309 * Board revision is coded in 4 GPIOs
311 u32
get_board_rev(void)
316 for (i
= 0, rev
= 0; i
< 4; i
++)
317 rev
|= (gpio_get_value(IMX_GPIO_NR(2, 12 + i
)) << i
);
322 int board_spi_cs_gpio(unsigned bus
, unsigned cs
)
324 if (bus
!= 2 || (cs
!= 0))
327 return IMX_GPIO_NR(4, 24);
330 int board_eth_init(bd_t
*bis
)
334 return cpu_eth_init(bis
);
337 int board_early_init_f(void)
346 /* address of boot parameters */
347 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
349 #ifdef CONFIG_SYS_I2C_MXC
350 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info
);
353 #ifdef CONFIG_MXC_SPI
359 #ifdef CONFIG_CMD_NAND
366 #ifdef CONFIG_CMD_BMODE
368 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
369 * see Table 8-11 and Table 5-9
370 * BOOT_CFG1[7] = 1 (boot from NAND)
371 * BOOT_CFG1[5] = 0 - raw NAND
372 * BOOT_CFG1[4] = 0 - default pad settings
373 * BOOT_CFG1[3:2] = 00 - devices = 1
374 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
375 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
376 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
377 * BOOT_CFG2[0] = 0 - Reset time 12ms
379 static const struct boot_mode board_boot_modes
[] = {
380 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
381 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
382 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
387 int board_late_init(void)
390 #ifdef CONFIG_CMD_BMODE
391 add_board_boot_modes(board_boot_modes
);
394 snprintf(buf
, sizeof(buf
), "%d", get_board_rev());
395 env_set("board_rev", buf
);
400 #ifdef CONFIG_SPL_BUILD
401 #include <asm/arch/mx6-ddr.h>
405 #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
406 static void phyflex_err006282_workaround(void)
409 * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
410 * to the CMIC. If this pin isn't toggled within 10s the boards
411 * reset. The pin is unconnected on older boards, so we do not
412 * need a check for older boards before applying this fixup.
415 gpio_direction_output(MX6_PHYFLEX_ERR006282
, 0);
417 gpio_direction_output(MX6_PHYFLEX_ERR006282
, 1);
419 gpio_set_value(MX6_PHYFLEX_ERR006282
, 0);
421 gpio_direction_input(MX6_PHYFLEX_ERR006282
);
424 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs
= {
425 .dram_sdclk_0
= 0x00000030,
426 .dram_sdclk_1
= 0x00000030,
427 .dram_cas
= 0x00000030,
428 .dram_ras
= 0x00000030,
429 .dram_reset
= 0x00000030,
430 .dram_sdcke0
= 0x00003000,
431 .dram_sdcke1
= 0x00003000,
432 .dram_sdba2
= 0x00000030,
433 .dram_sdodt0
= 0x00000030,
434 .dram_sdodt1
= 0x00000030,
436 .dram_sdqs0
= 0x00000028,
437 .dram_sdqs1
= 0x00000028,
438 .dram_sdqs2
= 0x00000028,
439 .dram_sdqs3
= 0x00000028,
440 .dram_sdqs4
= 0x00000028,
441 .dram_sdqs5
= 0x00000028,
442 .dram_sdqs6
= 0x00000028,
443 .dram_sdqs7
= 0x00000028,
444 .dram_dqm0
= 0x00000028,
445 .dram_dqm1
= 0x00000028,
446 .dram_dqm2
= 0x00000028,
447 .dram_dqm3
= 0x00000028,
448 .dram_dqm4
= 0x00000028,
449 .dram_dqm5
= 0x00000028,
450 .dram_dqm6
= 0x00000028,
451 .dram_dqm7
= 0x00000028,
454 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs
= {
455 .grp_ddr_type
= 0x000C0000,
456 .grp_ddrmode_ctl
= 0x00020000,
457 .grp_ddrpke
= 0x00000000,
458 .grp_addds
= IMX6Q_DRIVE_STRENGTH
,
459 .grp_ctlds
= IMX6Q_DRIVE_STRENGTH
,
460 .grp_ddrmode
= 0x00020000,
461 .grp_b0ds
= 0x00000028,
462 .grp_b1ds
= 0x00000028,
463 .grp_b2ds
= 0x00000028,
464 .grp_b3ds
= 0x00000028,
465 .grp_b4ds
= 0x00000028,
466 .grp_b5ds
= 0x00000028,
467 .grp_b6ds
= 0x00000028,
468 .grp_b7ds
= 0x00000028,
471 static const struct mx6_mmdc_calibration mx6_mmcd_calib
= {
472 .p0_mpwldectrl0
= 0x00110011,
473 .p0_mpwldectrl1
= 0x00240024,
474 .p1_mpwldectrl0
= 0x00260038,
475 .p1_mpwldectrl1
= 0x002C0038,
476 .p0_mpdgctrl0
= 0x03400350,
477 .p0_mpdgctrl1
= 0x03440340,
478 .p1_mpdgctrl0
= 0x034C0354,
479 .p1_mpdgctrl1
= 0x035C033C,
480 .p0_mprddlctl
= 0x322A2A2A,
481 .p1_mprddlctl
= 0x302C2834,
482 .p0_mpwrdlctl
= 0x34303834,
483 .p1_mpwrdlctl
= 0x422A3E36,
486 /* Index in RAM Chip array */
493 static struct mx6_ddr3_cfg mt41k_xx
[] = {
494 /* MT41K64M16JT-125 (1Gb density) */
509 /* MT41K256M16JT-125 (2Gb density) */
524 /* MT41K256M16JT-125 (4Gb density) */
540 static void ccgr_init(void)
542 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
544 writel(0x00C03F3F, &ccm
->CCGR0
);
545 writel(0x0030FC03, &ccm
->CCGR1
);
546 writel(0x0FFFC000, &ccm
->CCGR2
);
547 writel(0x3FF00000, &ccm
->CCGR3
);
548 writel(0x00FFF300, &ccm
->CCGR4
);
549 writel(0x0F0000C3, &ccm
->CCGR5
);
550 writel(0x000003FF, &ccm
->CCGR6
);
553 static void gpr_init(void)
555 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
557 /* enable AXI cache for VDOA/VPU/IPU */
558 writel(0xF00000CF, &iomux
->gpr
[4]);
559 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
560 writel(0x007F007F, &iomux
->gpr
[6]);
561 writel(0x007F007F, &iomux
->gpr
[7]);
564 static void spl_dram_init(struct mx6_ddr3_cfg
*mem_ddr
)
566 struct mx6_ddr_sysinfo sysinfo
= {
567 /* width of data bus:0=16,1=32,2=64 */
569 /* config for full 4GB range so that get_mem_size() works */
570 .cs_density
= 32, /* 32Gb per CS */
571 /* single chip select */
574 .rtt_wr
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
575 .rtt_nom
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
576 .walat
= 1, /* Write additional latency */
577 .ralat
= 5, /* Read additional latency */
578 .mif3_mode
= 3, /* Command prediction working mode */
579 .bi_on
= 1, /* Bank interleaving enabled */
580 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
581 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
582 .ddr_type
= DDR_TYPE_DDR3
,
583 .refsel
= 1, /* Refresh cycles at 32KHz */
584 .refr
= 7, /* 8 refresh commands per refresh cycle */
587 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs
, &mx6_grp_ioregs
);
588 mx6_dram_cfg(&sysinfo
, &mx6_mmcd_calib
, mem_ddr
);
591 int board_mmc_init(bd_t
*bis
)
593 if (spl_boot_device() == BOOT_DEVICE_SPI
)
594 printf("MMC SEtup, Boot SPI");
596 SETUP_IOMUX_PADS(usdhc3_pads
);
597 usdhc_cfg
[0].esdhc_base
= USDHC3_BASE_ADDR
;
598 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
599 usdhc_cfg
[0].max_bus_width
= 4;
600 gd
->arch
.sdhc_clk
= usdhc_cfg
[0].sdhc_clk
;
602 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[0]);
606 void board_boot_order(u32
*spl_boot_list
)
608 spl_boot_list
[0] = spl_boot_device();
609 printf("Boot device %x\n", spl_boot_list
[0]);
610 switch (spl_boot_list
[0]) {
611 case BOOT_DEVICE_SPI
:
612 spl_boot_list
[1] = BOOT_DEVICE_UART
;
614 case BOOT_DEVICE_MMC1
:
615 spl_boot_list
[1] = BOOT_DEVICE_SPI
;
616 spl_boot_list
[2] = BOOT_DEVICE_UART
;
619 printf("Boot device %x\n", spl_boot_list
[0]);
624 * This is used because get_ram_size() does not
625 * take care of cache, resulting a wrong size
626 * pfla02 has just 1, 2 or 4 GB option
627 * Function checks for mirrors in the first CS
629 #define RAM_TEST_PATTERN 0xaa5555aa
630 static unsigned int pfla02_detect_ramsize(void)
633 unsigned int offset
= 512 * 1024 * 1024;
636 for (i
= 0; i
< 2; i
++) {
637 p
= (u32
*)PHYS_SDRAM
;
638 p1
= (u32
*)(PHYS_SDRAM
+ (i
+ 1) * offset
);
641 *p
= RAM_TEST_PATTERN
;
644 * This is required to detect mirroring
645 * else we read back values from cache
655 void board_init_f(ulong dummy
)
657 unsigned int ramchip
;
658 #ifdef CONFIG_CMD_NAND
663 /* setup clock gating */
666 /* setup AIPS and disable watchdog */
672 board_early_init_f();
677 /* UART clocks enabled and gd valid - init serial console */
678 preloader_console_init();
684 /* DDR initialization */
685 spl_dram_init(&mt41k_xx
[RAM_4GB
]);
686 ramchip
= pfla02_detect_ramsize();
687 if (ramchip
!= RAM_4GB
)
688 spl_dram_init(&mt41k_xx
[ramchip
]);
691 memset(__bss_start
, 0, __bss_end
- __bss_start
);
693 phyflex_err006282_workaround();
695 /* load/boot image from boot device */
696 board_init_r(NULL
, 0);