2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 #if defined(CONFIG_DDR_ECC)
35 extern void ddr_enable_ecc(unsigned int dram_size
);
38 extern long int spd_sdram(void);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
45 int board_early_init_f (void)
47 #if defined(CONFIG_PCI)
48 volatile ccsr_pcix_t
*pci
= (void *)(CFG_MPC85xx_PCIX_ADDR
);
50 pci
->peer
&= 0xffffffdf; /* disable master abort */
58 puts("Board: MicroSys PM854\n");
61 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
62 CONFIG_SYS_CLK_FREQ
/ 1000000);
64 printf(" PCI1: disabled\n");
68 * Initialize local bus.
77 initdram(int board_type
)
80 extern long spd_sdram (void);
82 puts("Initializing\n");
84 #if defined(CONFIG_DDR_DLL)
86 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
92 * Work around to stabilize DDR DLL
94 gur
->ddrdllcr
= 0x81000000;
95 asm("sync;isync;msync");
97 while (gur
->ddrdllcr
!= 0x81000100)
99 gur
->devdisr
= gur
->devdisr
| 0x00010000;
100 asm("sync;isync;msync");
103 gur
->devdisr
= gur
->devdisr
& 0xfff7ffff;
104 asm("sync;isync;msync");
110 #if defined(CONFIG_SPD_EEPROM)
111 dram_size
= spd_sdram ();
113 dram_size
= fixed_sdram ();
116 #if defined(CONFIG_DDR_ECC)
118 * Initialize and enable DDR ECC.
120 ddr_enable_ecc(dram_size
);
128 * Initialize Local Bus
134 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
135 volatile ccsr_lbc_t
*lbc
= (void *)(CFG_MPC85xx_LBC_ADDR
);
143 * Fix Local Bus clock glitch when DLL is enabled.
145 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
146 * If localbus freq is > 133Mhz, DLL can be safely enabled.
147 * Between 66 and 133, the DLL is enabled with an override workaround.
150 get_sys_info(&sysinfo
);
151 clkdiv
= lbc
->lcrr
& 0x0f;
152 lbc_hz
= sysinfo
.freqSystemBus
/ 1000000 / clkdiv
;
155 lbc
->lcrr
= CFG_LBC_LCRR
| 0x80000000; /* DLL Bypass */
157 } else if (lbc_hz
>= 133) {
158 lbc
->lcrr
= CFG_LBC_LCRR
& (~0x80000000); /* DLL Enabled */
162 * On REV1 boards, need to change CLKDIV before enable DLL.
163 * Default CLKDIV is 8, change it to 4 temporarily.
165 uint pvr
= get_pvr();
166 uint temp_lbcdll
= 0;
168 if (pvr
== PVR_85xx_REV1
) {
169 /* FIXME: Justify the high bit here. */
170 lbc
->lcrr
= 0x10000004;
173 lbc
->lcrr
= CFG_LBC_LCRR
& (~0x80000000); /* DLL Enabled */
177 * Sample LBC DLL ctrl reg, upshift it to set the
180 temp_lbcdll
= gur
->lbcdllcr
;
181 gur
->lbcdllcr
= (((temp_lbcdll
& 0xff) << 16) | 0x80000000);
182 asm("sync;isync;msync");
187 #if defined(CFG_DRAM_TEST)
190 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
191 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
194 printf("SDRAM test phase 1:\n");
195 for (p
= pstart
; p
< pend
; p
++)
198 for (p
= pstart
; p
< pend
; p
++) {
199 if (*p
!= 0xaaaaaaaa) {
200 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
205 printf("SDRAM test phase 2:\n");
206 for (p
= pstart
; p
< pend
; p
++)
209 for (p
= pstart
; p
< pend
; p
++) {
210 if (*p
!= 0x55555555) {
211 printf ("SDRAM test fails at: %08x\n", (uint
) p
);
216 printf("SDRAM test passed.\n");
222 #if !defined(CONFIG_SPD_EEPROM)
223 /*************************************************************************
224 * fixed sdram init -- doesn't use serial presence detect.
225 ************************************************************************/
226 long int fixed_sdram (void)
229 volatile ccsr_ddr_t
*ddr
= (void *)(CFG_MPC85xx_DDR_ADDR
);
231 ddr
->cs0_bnds
= CFG_DDR_CS0_BNDS
;
232 ddr
->cs0_config
= CFG_DDR_CS0_CONFIG
;
233 ddr
->timing_cfg_1
= CFG_DDR_TIMING_1
;
234 ddr
->timing_cfg_2
= CFG_DDR_TIMING_2
;
235 ddr
->sdram_mode
= CFG_DDR_MODE
;
236 ddr
->sdram_interval
= CFG_DDR_INTERVAL
;
237 #if defined (CONFIG_DDR_ECC)
238 ddr
->err_disable
= 0x0000000D;
239 ddr
->err_sbe
= 0x00ff0000;
241 asm("sync;isync;msync");
243 #if defined (CONFIG_DDR_ECC)
244 /* Enable ECC checking */
245 ddr
->sdram_cfg
= (CFG_DDR_CONTROL
| 0x20000000);
247 ddr
->sdram_cfg
= CFG_DDR_CONTROL
;
249 asm("sync; isync; msync");
252 return CFG_SDRAM_SIZE
* 1024 * 1024;
254 #endif /* !defined(CONFIG_SPD_EEPROM) */
257 #if defined(CONFIG_PCI)
259 * Initialize PCI Devices, report devices found.
262 #ifndef CONFIG_PCI_PNP
263 static struct pci_config_table pci_pm854_config_table
[] = {
264 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
265 PCI_IDSEL_NUMBER
, PCI_ANY_ID
,
266 pci_cfgfunc_config_device
, { PCI_ENET0_IOADDR
,
268 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
275 static struct pci_controller hose
= {
276 #ifndef CONFIG_PCI_PNP
277 config_table
: pci_pm854_config_table
,
281 #endif /* CONFIG_PCI */
288 pci_mpc85xx_init(&hose
);
289 #endif /* CONFIG_PCI */