1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019, 2023 NXP
6 #include <linux/kernel.h>
7 #include <asm/arch/ddr.h>
9 struct dram_cfg_param ddr_ddrc_cfg
[] = {
10 /** Initialize DDRC registers **/
13 { 0x3d400000, 0xa1080020 },
14 { 0x3d400020, 0x1323 },
15 { 0x3d400024, 0x1c61a00 },
16 { 0x3d400064, 0x710105 },
17 { 0x3d400070, 0x61027f10 },
18 { 0x3d400074, 0x7b0 },
19 { 0x3d4000d0, 0xc003071a },
20 { 0x3d4000d4, 0xb70000 },
21 { 0x3d4000dc, 0xe40036 },
22 { 0x3d4000e0, 0x330000 },
23 { 0x3d4000e8, 0x660048 },
24 { 0x3d4000ec, 0x160048 },
25 { 0x3d400100, 0x1e261f28 },
26 { 0x3d400104, 0x7073b },
27 { 0x3d40010c, 0xe0e000 },
28 { 0x3d400110, 0x11040a11 },
29 { 0x3d400114, 0x2050e0e },
30 { 0x3d400118, 0x1010008 },
31 { 0x3d40011c, 0x501 },
32 { 0x3d400130, 0x20700 },
33 { 0x3d400134, 0xe100002 },
34 { 0x3d400138, 0x10c },
35 { 0x3d400144, 0xba005d },
36 { 0x3d400180, 0x3a2001c },
37 { 0x3d400184, 0x2f07187 },
39 { 0x3d400190, 0x49b820c },
40 { 0x3d400194, 0x80303 },
41 { 0x3d4001b4, 0x1b0c },
42 { 0x3d4001a0, 0xe0400018 },
43 { 0x3d4001a4, 0xdf00e4 },
44 { 0x3d4001a8, 0x80000000 },
48 { 0x3d4000f4, 0xc99 },
49 { 0x3d400108, 0x810191a },
52 { 0x3d400210, 0x1f1f },
53 { 0x3d400204, 0x80808 },
54 { 0x3d400214, 0x7070707 },
55 { 0x3d400218, 0x7070707 },
56 { 0x3d40021c, 0xf0f },
57 { 0x3d400250, 0x1705 },
59 { 0x3d40025c, 0x4000030 },
60 { 0x3d400264, 0x900093e7 },
61 { 0x3d40026c, 0x2005574 },
62 { 0x3d400400, 0x111 },
63 { 0x3d400404, 0x72ff },
64 { 0x3d400408, 0x72ff },
65 { 0x3d400494, 0x2100e07 },
66 { 0x3d400498, 0x620096 },
67 { 0x3d40049c, 0x1100e07 },
68 { 0x3d4004a0, 0xc8012c },
69 { 0x3d402020, 0x1021 },
70 { 0x3d402024, 0x30d400 },
71 { 0x3d402050, 0x20d000 },
72 { 0x3d402064, 0xc001c },
73 { 0x3d4020dc, 0x840000 },
74 { 0x3d4020e0, 0x330000 },
75 { 0x3d4020e8, 0x660048 },
76 { 0x3d4020ec, 0x160048 },
77 { 0x3d402100, 0xa040305 },
78 { 0x3d402104, 0x30407 },
79 { 0x3d402108, 0x203060b },
80 { 0x3d40210c, 0x505000 },
81 { 0x3d402110, 0x2040202 },
82 { 0x3d402114, 0x2030202 },
83 { 0x3d402118, 0x1010004 },
84 { 0x3d40211c, 0x301 },
85 { 0x3d402130, 0x20300 },
86 { 0x3d402134, 0xa100002 },
88 { 0x3d402144, 0x14000a },
89 { 0x3d402180, 0x640004 },
90 { 0x3d402190, 0x3818200 },
91 { 0x3d402194, 0x80303 },
92 { 0x3d4021b4, 0x100 },
93 { 0x3d4020f4, 0xc99 },
94 { 0x3d403020, 0x1021 },
95 { 0x3d403024, 0xc3500 },
96 { 0x3d403050, 0x20d000 },
97 { 0x3d403064, 0x30007 },
98 { 0x3d4030dc, 0x840000 },
99 { 0x3d4030e0, 0x330000 },
100 { 0x3d4030e8, 0x660048 },
101 { 0x3d4030ec, 0x160048 },
102 { 0x3d403100, 0xa010102 },
103 { 0x3d403104, 0x30404 },
104 { 0x3d403108, 0x203060b },
105 { 0x3d40310c, 0x505000 },
106 { 0x3d403110, 0x2040202 },
107 { 0x3d403114, 0x2030202 },
108 { 0x3d403118, 0x1010004 },
109 { 0x3d40311c, 0x301 },
110 { 0x3d403130, 0x20300 },
111 { 0x3d403134, 0xa100002 },
113 { 0x3d403144, 0x50003 },
114 { 0x3d403180, 0x190004 },
115 { 0x3d403190, 0x3818200 },
116 { 0x3d403194, 0x80303 },
117 { 0x3d4031b4, 0x100 },
118 { 0x3d4030f4, 0xc99 },
122 /* PHY Initialize Configuration */
123 struct dram_cfg_param ddr_ddrphy_cfg
[] = {
331 /* ddr phy trained csr */
332 struct dram_cfg_param ddr_ddrphy_trained_csr
[] = {
1054 /* P0 message block paremeter for training firmware */
1055 struct dram_cfg_param ddr_fsp0_cfg
[] = {
1059 { 0x54005, 0x2228 },
1061 { 0x54008, 0x131f },
1066 { 0x54019, 0x36e4 },
1068 { 0x5401b, 0x4866 },
1069 { 0x5401c, 0x4800 },
1071 { 0x5401f, 0x36e4 },
1073 { 0x54021, 0x4866 },
1074 { 0x54022, 0x4800 },
1076 { 0x5402b, 0x1000 },
1078 { 0x54032, 0xe400 },
1079 { 0x54033, 0x3336 },
1080 { 0x54034, 0x6600 },
1083 { 0x54037, 0x1600 },
1084 { 0x54038, 0xe400 },
1085 { 0x54039, 0x3336 },
1086 { 0x5403a, 0x6600 },
1089 { 0x5403d, 0x1600 },
1093 /* P1 message block paremeter for training firmware */
1094 struct dram_cfg_param ddr_fsp1_cfg
[] = {
1099 { 0x54005, 0x2228 },
1101 { 0x54008, 0x121f },
1108 { 0x5401b, 0x4866 },
1109 { 0x5401c, 0x4800 },
1113 { 0x54021, 0x4866 },
1114 { 0x54022, 0x4800 },
1116 { 0x5402b, 0x1000 },
1118 { 0x54032, 0x8400 },
1119 { 0x54033, 0x3300 },
1120 { 0x54034, 0x6600 },
1123 { 0x54037, 0x1600 },
1124 { 0x54038, 0x8400 },
1125 { 0x54039, 0x3300 },
1126 { 0x5403a, 0x6600 },
1129 { 0x5403d, 0x1600 },
1133 /* P2 message block paremeter for training firmware */
1134 struct dram_cfg_param ddr_fsp2_cfg
[] = {
1139 { 0x54005, 0x2228 },
1141 { 0x54008, 0x121f },
1148 { 0x5401b, 0x4866 },
1149 { 0x5401c, 0x4800 },
1153 { 0x54021, 0x4866 },
1154 { 0x54022, 0x4800 },
1156 { 0x5402b, 0x1000 },
1158 { 0x54032, 0x8400 },
1159 { 0x54033, 0x3300 },
1160 { 0x54034, 0x6600 },
1163 { 0x54037, 0x1600 },
1164 { 0x54038, 0x8400 },
1165 { 0x54039, 0x3300 },
1166 { 0x5403a, 0x6600 },
1169 { 0x5403d, 0x1600 },
1173 /* P0 2D message block paremeter for training firmware */
1174 struct dram_cfg_param ddr_fsp0_2d_cfg
[] = {
1178 { 0x54005, 0x2228 },
1184 { 0x54010, 0x1f7f },
1186 { 0x54019, 0x36e4 },
1188 { 0x5401b, 0x4866 },
1189 { 0x5401c, 0x4800 },
1191 { 0x5401f, 0x36e4 },
1193 { 0x54021, 0x4866 },
1194 { 0x54022, 0x4800 },
1196 { 0x5402b, 0x1000 },
1198 { 0x54032, 0xe400 },
1199 { 0x54033, 0x3336 },
1200 { 0x54034, 0x6600 },
1203 { 0x54037, 0x1600 },
1204 { 0x54038, 0xe400 },
1205 { 0x54039, 0x3336 },
1206 { 0x5403a, 0x6600 },
1209 { 0x5403d, 0x1600 },
1213 /* DRAM PHY init engine image */
1214 struct dram_cfg_param ddr_phy_pie
[] = {
1273 { 0x9005c, 0x40c0 },
1279 { 0x90062, 0x4040 },
1349 { 0x40001, 0x4008 },
1353 { 0x40002, 0x4040 },
1363 { 0x40044, 0x1740 },
1371 { 0x40046, 0x2001 },
1375 { 0x40047, 0x2800 },
1383 { 0x40049, 0x1400 },
1393 { 0x4000c, 0x4028 },
1405 { 0x4000f, 0x4040 },
1409 { 0x40010, 0x2604 },
1416 { 0x40071, 0x2002 },
1421 { 0x40013, 0x2604 },
1428 { 0x40074, 0x2002 },
1429 { 0x40015, 0x4040 },
1435 { 0x40056, 0x1200 },
1439 { 0x40057, 0x1300 },
1443 { 0x40058, 0x1200 },
1447 { 0x40059, 0x1300 },
1449 { 0x4001a, 0x4808 },
1490 { 0x900c9, 0x8568 },
1499 { 0x900d2, 0x8558 },
1504 { 0x900d7, 0x1ff8 },
1505 { 0x900d8, 0x85a8 },
1514 { 0x900e1, 0x8310 },
1517 { 0x900e4, 0xa310 },
1529 { 0x900f0, 0x8310 },
1532 { 0x900f3, 0xa310 },
1534 { 0x900f5, 0x1ff8 },
1535 { 0x900f6, 0x85a8 },
1547 { 0x90102, 0x8b10 },
1550 { 0x90105, 0xab10 },
1562 { 0x90111, 0x8b10 },
1565 { 0x90114, 0xab10 },
1580 { 0x90123, 0x8080 },
1595 { 0x90132, 0x8080 },
1601 { 0x90138, 0x8568 },
1610 { 0x90141, 0x8558 },
1622 { 0x9014d, 0x8558 },
1637 { 0x9015c, 0x8140 },
1640 { 0x9015f, 0x8138 },
1664 { 0x90177, 0x8140 },
1710 { 0x9000f, 0x6110 },
1711 { 0x90010, 0x2152 },
1712 { 0x90011, 0xdfbd },
1713 { 0x90012, 0x2060 },
1714 { 0x90013, 0x6152 },
1740 { 0x10002, 0x6209 },
1754 { 0x11002, 0x6209 },
1768 { 0x12002, 0x6209 },
1782 { 0x13002, 0x6209 },
1798 struct dram_fsp_msg ddr_dram_fsp_msg
[] = {
1802 .fw_type
= FW_1D_IMAGE
,
1803 .fsp_cfg
= ddr_fsp0_cfg
,
1804 .fsp_cfg_num
= ARRAY_SIZE(ddr_fsp0_cfg
),
1809 .fw_type
= FW_1D_IMAGE
,
1810 .fsp_cfg
= ddr_fsp1_cfg
,
1811 .fsp_cfg_num
= ARRAY_SIZE(ddr_fsp1_cfg
),
1816 .fw_type
= FW_1D_IMAGE
,
1817 .fsp_cfg
= ddr_fsp2_cfg
,
1818 .fsp_cfg_num
= ARRAY_SIZE(ddr_fsp2_cfg
),
1823 .fw_type
= FW_2D_IMAGE
,
1824 .fsp_cfg
= ddr_fsp0_2d_cfg
,
1825 .fsp_cfg_num
= ARRAY_SIZE(ddr_fsp0_2d_cfg
),
1829 /* ddr timing config params */
1830 struct dram_timing_info dram_timing
= {
1831 .ddrc_cfg
= ddr_ddrc_cfg
,
1832 .ddrc_cfg_num
= ARRAY_SIZE(ddr_ddrc_cfg
),
1833 .ddrphy_cfg
= ddr_ddrphy_cfg
,
1834 .ddrphy_cfg_num
= ARRAY_SIZE(ddr_ddrphy_cfg
),
1835 .fsp_msg
= ddr_dram_fsp_msg
,
1836 .fsp_msg_num
= ARRAY_SIZE(ddr_dram_fsp_msg
),
1837 .ddrphy_trained_csr
= ddr_ddrphy_trained_csr
,
1838 .ddrphy_trained_csr_num
= ARRAY_SIZE(ddr_ddrphy_trained_csr
),
1839 .ddrphy_pie
= ddr_phy_pie
,
1840 .ddrphy_pie_num
= ARRAY_SIZE(ddr_phy_pie
),
1841 .fsp_table
= { 3732, 400, 100, },