1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux-mx28.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15 #include <linux/mii.h>
20 DECLARE_GLOBAL_DATA_PTR
;
25 int board_early_init_f(void)
27 /* IO0 clock at 480MHz */
28 mxs_set_ioclk(MXC_IOCLK0
, 480000);
29 /* IO1 clock at 480MHz */
30 mxs_set_ioclk(MXC_IOCLK1
, 480000);
32 /* SSP2 clock at 160MHz */
33 mxs_set_sspclk(MXC_SSPCLK2
, 160000, 0);
40 return mxs_dram_init();
45 /* Adress of boot parameters */
46 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
52 int board_eth_init(bd_t
*bis
)
54 struct mxs_clkctrl_regs
*clkctrl_regs
=
55 (struct mxs_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
56 struct eth_device
*dev
;
59 ret
= cpu_eth_init(bis
);
61 /* BG0900 uses ENET_CLK PAD to drive FEC clock */
62 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK
| CLKCTRL_ENET_CLK_OUT_EN
,
63 &clkctrl_regs
->hw_clkctrl_enet
);
66 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13
, 0);
68 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13
, 1);
70 ret
= fecmxc_initialize_multi(bis
, 0, 0, MXS_ENET0_BASE
);
72 puts("FEC MXS: Unable to init FEC0\n");
76 dev
= eth_get_dev_by_name("FEC0");
78 puts("FEC MXS: Unable to get FEC0 device entry\n");