3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
28 #include <spd_sdram.h>
29 #include <asm/ppc4xx-emac.h>
31 #include <asm/processor.h>
32 #include <asm/4xx_pci.h>
34 DECLARE_GLOBAL_DATA_PTR
;
36 extern int alpr_fpga_init(void);
38 int board_early_init_f (void)
40 /*-------------------------------------------------------------------------
41 * Initialize EBC CONFIG
42 *-------------------------------------------------------------------------*/
43 mtebc(EBC0_CFG
, EBC_CFG_LE_UNLOCK
|
44 EBC_CFG_PTD_DISABLE
| EBC_CFG_RTC_64PERCLK
|
45 EBC_CFG_ATC_PREVIOUS
| EBC_CFG_DTC_PREVIOUS
|
46 EBC_CFG_CTC_PREVIOUS
| EBC_CFG_EMC_NONDEFAULT
|
47 EBC_CFG_PME_DISABLE
| EBC_CFG_PR_32
);
49 /*--------------------------------------------------------------------
50 * Setup the interrupt controller polarities, triggers, etc.
51 *-------------------------------------------------------------------*/
53 * Because of the interrupt handling rework to handle 440GX interrupts
54 * with the common code, we needed to change names of the UIC registers.
55 * Here the new relationship:
57 * U-Boot name 440GX name
58 * -----------------------
64 mtdcr (UIC1SR
, 0xffffffff); /* clear all */
65 mtdcr (UIC1ER
, 0x00000000); /* disable all */
66 mtdcr (UIC1CR
, 0x00000009); /* SMI & UIC1 crit are critical */
67 mtdcr (UIC1PR
, 0xfffffe03); /* per manual */
68 mtdcr (UIC1TR
, 0x01c00000); /* per manual */
69 mtdcr (UIC1VR
, 0x00000001); /* int31 highest, base=0x000 */
70 mtdcr (UIC1SR
, 0xffffffff); /* clear all */
72 mtdcr (UIC2SR
, 0xffffffff); /* clear all */
73 mtdcr (UIC2ER
, 0x00000000); /* disable all */
74 mtdcr (UIC2CR
, 0x00000000); /* all non-critical */
75 mtdcr (UIC2PR
, 0xffffe0ff); /* per ref-board manual */
76 mtdcr (UIC2TR
, 0x00ffc000); /* per ref-board manual */
77 mtdcr (UIC2VR
, 0x00000001); /* int31 highest, base=0x000 */
78 mtdcr (UIC2SR
, 0xffffffff); /* clear all */
80 mtdcr (UIC3SR
, 0xffffffff); /* clear all */
81 mtdcr (UIC3ER
, 0x00000000); /* disable all */
82 mtdcr (UIC3CR
, 0x00000000); /* all non-critical */
83 mtdcr (UIC3PR
, 0xffffffff); /* per ref-board manual */
84 mtdcr (UIC3TR
, 0x00ff8c0f); /* per ref-board manual */
85 mtdcr (UIC3VR
, 0x00000001); /* int31 highest, base=0x000 */
86 mtdcr (UIC3SR
, 0xffffffff); /* clear all */
88 mtdcr (UIC0SR
, 0xfc000000); /* clear all */
89 mtdcr (UIC0ER
, 0x00000000); /* disable all */
90 mtdcr (UIC0CR
, 0x00000000); /* all non-critical */
91 mtdcr (UIC0PR
, 0xfc000000); /* */
92 mtdcr (UIC0TR
, 0x00000000); /* */
93 mtdcr (UIC0VR
, 0x00000001); /* */
95 /* Setup shutdown/SSD empty interrupt as inputs */
96 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~(CONFIG_SYS_GPIO_SHUTDOWN
| CONFIG_SYS_GPIO_SSD_EMPTY
));
97 out32(GPIO0_ODR
, in32(GPIO0_ODR
) & ~(CONFIG_SYS_GPIO_SHUTDOWN
| CONFIG_SYS_GPIO_SSD_EMPTY
));
99 /* Setup GPIO/IRQ multiplexing */
100 mtsdr(SDR0_PFC0
, 0x01a33e00);
105 int last_stage_init(void)
110 * Configure LED's of both Marvell 88E1111 PHY's
112 * This has to be done after the 4xx ethernet driver is loaded,
113 * so "last_stage_init()" is the right place.
115 miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, ®
);
117 miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR
, 0x18, reg
);
118 miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, ®
);
120 miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR
, 0x18, reg
);
125 static int board_rev(void)
128 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~(CONFIG_SYS_GPIO_REV0
| CONFIG_SYS_GPIO_REV1
));
129 out32(GPIO0_ODR
, in32(GPIO0_ODR
) & ~(CONFIG_SYS_GPIO_REV0
| CONFIG_SYS_GPIO_REV1
));
131 return (in32(GPIO0_IR
) >> 16) & 0x3;
134 int checkboard (void)
137 int i
= getenv_f("serial#", buf
, sizeof(buf
));
139 printf ("Board: ALPR");
144 printf(" (Rev. %d)\n", board_rev());
149 #if defined(CONFIG_PCI)
151 * Override weak pci_pre_init()
153 int pci_pre_init(struct pci_controller
*hose
)
155 if (__pci_pre_init(hose
) == 0)
164 /*************************************************************************
165 * Override weak is_pci_host()
167 * This routine is called to determine if a pci scan should be
168 * performed. With various hardware environments (especially cPCI and
169 * PPMC) it's insufficient to depend on the state of the arbiter enable
170 * bit in the strap register, or generic host/adapter assumptions.
172 * Rather than hard-code a bad assumption in the general 440 code, the
173 * 440 pci code requires the board to decide at runtime.
175 * Return 0 for adapter mode, non-zero for host (monarch) mode.
178 ************************************************************************/
179 static void wait_for_pci_ready(void)
182 * Configure EREADY as input
184 out32(GPIO0_TCR
, in32(GPIO0_TCR
) & ~CONFIG_SYS_GPIO_EREADY
);
188 if (in32(GPIO0_IR
) & CONFIG_SYS_GPIO_EREADY
)
194 int is_pci_host(struct pci_controller
*hose
)
196 wait_for_pci_ready();
197 return 1; /* return 1 for host controller */
199 #endif /* defined(CONFIG_PCI) */
201 /*************************************************************************
204 ************************************************************************/
205 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
206 void pci_master_init(struct pci_controller
*hose
)
208 /*--------------------------------------------------------------------------+
209 | PowerPC440 PCI Master configuration.
210 | Map PLB/processor addresses to PCI memory space.
211 | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
212 | Use byte reversed out routines to handle endianess.
213 | Make this region non-prefetchable.
214 +--------------------------------------------------------------------------*/
215 out32r( PCIL0_POM0SA
, 0 ); /* disable */
216 out32r( PCIL0_POM1SA
, 0 ); /* disable */
217 out32r( PCIL0_POM2SA
, 0 ); /* disable */
219 out32r(PCIL0_POM0LAL
, CONFIG_SYS_PCI_MEMBASE
); /* PMM0 Local Address */
220 out32r(PCIL0_POM0LAH
, 0x00000003); /* PMM0 Local Address */
221 out32r(PCIL0_POM0PCIAL
, CONFIG_SYS_PCI_MEMBASE
); /* PMM0 PCI Low Address */
222 out32r(PCIL0_POM0PCIAH
, 0x00000000); /* PMM0 PCI High Address */
223 out32r(PCIL0_POM0SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
225 out32r(PCIL0_POM1LAL
, CONFIG_SYS_PCI_MEMBASE2
); /* PMM0 Local Address */
226 out32r(PCIL0_POM1LAH
, 0x00000003); /* PMM0 Local Address */
227 out32r(PCIL0_POM1PCIAL
, CONFIG_SYS_PCI_MEMBASE2
); /* PMM0 PCI Low Address */
228 out32r(PCIL0_POM1PCIAH
, 0x00000000); /* PMM0 PCI High Address */
229 out32r(PCIL0_POM1SA
, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
231 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */