board/prodrive/common/fpga.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2001-2004
   6  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   7  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/processor.h>
  14 #include <command.h>
  15
  16 /* ------------------------------------------------------------------------- */
  17
  18 #ifdef FPGA_DEBUG
  19 #define DBG(x...) printf(x)
  20 #else
  21 #define DBG(x...)
  22 #endif /* DEBUG */
  23
  24 #define FPGA_PRG                CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
  25 #define FPGA_CLK                CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output)    */
  26 #define FPGA_DATA               CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output)  */
  27 #define FPGA_DONE               CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input)   */
  28 #define FPGA_INIT               CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input)   */
  29
  30 #define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
  31 #define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
  32 #define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
  33
  34 #ifndef OLD_VAL
  35 # define OLD_VAL                0
  36 #endif
  37
  38 #if 0 /* test-only */
  39 #define FPGA_WRITE_1 { \
  40                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */ \
  41                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */      \
  42                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */      \
  43                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
  44
  45 #define FPGA_WRITE_0 { \
  46                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set clock to 0 */      \
  47                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );  /* set data to 0  */      \
  48                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );  /* set clock to 1 */      \
  49                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
  50 #else
  51 #define FPGA_WRITE_1 { \
  52                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | FPGA_DATA);  /* set data to 1  */      \
  53                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
  54
  55 #define FPGA_WRITE_0 { \
  56                 SET_FPGA(OLD_VAL | FPGA_PRG | 0        | 0        );   /* set data to 0  */     \
  57                 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0        );}  /* set data to 1  */
  58 #endif
  59
  60 static int fpga_boot(unsigned char *fpgadata, int size)
  61 {
  62         int i,index,len;
  63         int count;
  64         int j;
  65
  66         /* display infos on fpgaimage */
  67         index = 15;
  68         for (i=0; i<4; i++) {
  69                 len = fpgadata[index];
  70                 DBG("FPGA: %s\n", &(fpgadata[index+1]));
  71                 index += len+3;
  72         }
  73
  74         /* search for preamble 0xFFFFFFFF */
  75         while (1) {
  76                 if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
  77                     (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
  78                         break; /* preamble found */
  79                 else
  80                         index++;
  81         }
  82
  83         DBG("FPGA: configdata starts at position 0x%x\n",index);
  84         DBG("FPGA: length of fpga-data %d\n", size-index);
  85
  86         /*
  87          * Setup port pins for fpga programming
  88          */
  89         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);            /* set pins to high */
  90
  91         DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
  92         DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
  93
  94         /*
  95          * Init fpga by asserting and deasserting PROGRAM*
  96          */
  97         SET_FPGA(0 | FPGA_CLK | FPGA_DATA);             /* set prog active */
  98
  99         /* Wait for FPGA init line low */
 100         count = 0;
 101         while (FPGA_INIT_STATE) {
 102                 udelay(1000); /* wait 1ms */
 103                 /* Check for timeout - 100us max, so use 3ms */
 104                 if (count++ > 3) {
 105                         DBG("FPGA: Booting failed!\n");
 106                         return ERROR_FPGA_PRG_INIT_LOW;
 107                 }
 108         }
 109
 110         DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
 111         DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
 112
 113         /* deassert PROGRAM* */
 114         SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);           /* set prog inactive */
 115
 116         /* Wait for FPGA end of init period .  */
 117         count = 0;
 118         while (!(FPGA_INIT_STATE)) {
 119                 udelay(1000); /* wait 1ms */
 120                 /* Check for timeout */
 121                 if (count++ > 3) {
 122                         DBG("FPGA: Booting failed!\n");
 123                         return ERROR_FPGA_PRG_INIT_HIGH;
 124                 }
 125         }
 126
 127         DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
 128         DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
 129
 130         DBG("write configuration data into fpga\n");
 131         /* write configuration-data into fpga... */
 132
 133         /*
 134          * Load uncompressed image into fpga
 135          */
 136         for (i=index; i<size; i++) {
 137                 for (j=0; j<8; j++) {
 138                         if ((fpgadata[i] & 0x80) == 0x80) {
 139                                 FPGA_WRITE_1;
 140                         } else {
 141                                 FPGA_WRITE_0;
 142                         }
 143                         fpgadata[i] <<= 1;
 144                 }
 145         }
 146
 147         DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
 148         DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
 149
 150         /*
 151          * Check if fpga's DONE signal - correctly booted ?
 152          */
 153
 154         /* Wait for FPGA end of programming period .  */
 155         count = 0;
 156         while (!(FPGA_DONE_STATE)) {
 157                 udelay(1000); /* wait 1ms */
 158                 /* Check for timeout */
 159                 if (count++ > 3) {
 160                         DBG("FPGA: Booting failed!\n");
 161                         return ERROR_FPGA_PRG_DONE;
 162                 }
 163         }
 164
 165         DBG("FPGA: Booting successful!\n");
 166         return 0;
 167 }