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[people/ms/u-boot.git] / board / prodrive / p3mx / p3mx.c
1 /*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Based on original work by
6 * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
7 * Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
28 * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
29 * modifications for the P3M750 by roel.loeffen@prodrive.nl
30 */
31
32 /*
33 * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
34 */
35
36 #include <common.h>
37 #include <74xx_7xx.h>
38 #include "../../Marvell/include/memory.h"
39 #include "../../Marvell/include/pci.h"
40 #include "../../Marvell/include/mv_gen_reg.h"
41 #include <net.h>
42 #include <i2c.h>
43
44 #include "eth.h"
45 #include "mpsc.h"
46 #include "64460.h"
47 #include "mv_regs.h"
48 #include "p3mx.h"
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 #undef DEBUG
53 /*#define DEBUG */
54
55 #ifdef CONFIG_PCI
56 #define MAP_PCI
57 #endif /* of CONFIG_PCI */
58
59 #ifdef DEBUG
60 #define DP(x) x
61 #else
62 #define DP(x)
63 #endif
64
65 extern flash_info_t flash_info[];
66
67 /* ------------------------------------------------------------------------- */
68
69 /* this is the current GT register space location */
70 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
71
72 /* Unfortunately, we cant change it while we are in flash, so we initialize it
73 * to the "final" value. This means that any debug_led calls before
74 * board_early_init_f wont work right (like in cpu_init_f).
75 * See also my_remap_gt_regs below. (NTL)
76 */
77
78 void board_prebootm_init (void);
79 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
80 int display_mem_map (void);
81 void set_led(int);
82
83 /* ------------------------------------------------------------------------- */
84
85 /*
86 * This is a version of the GT register space remapping function that
87 * doesn't touch globals (meaning, it's ok to run from flash.)
88 *
89 * Unfortunately, this has the side effect that a writable
90 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
91 */
92
93 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
94 {
95 u32 temp;
96
97 /* check and see if it's already moved */
98 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
99 if ((temp & 0xffff) == new_loc >> 16)
100 return;
101
102 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
103 0xffff0000) | (new_loc >> 16);
104
105 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
106
107 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
108 }
109
110 #ifdef CONFIG_PCI
111
112 static void gt_pci_config (void)
113 {
114 unsigned int stat;
115 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */
116 /* FuncNum 10:8, RegNum 7:2 */
117
118 /*
119 * In PCIX mode devices provide their own bus and device numbers.
120 * We query the Discovery II's
121 * config registers by writing ones to the bus and device.
122 * We then update the Virtual register with the correct value for the
123 * bus and device.
124 */
125 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
126 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
127
128 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
129
130 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
131 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
132 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
133
134 }
135 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
136 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
137 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
138
139 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
140 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
141 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
142 }
143
144 /* Enable master */
145 PCI_MASTER_ENABLE (0, SELF);
146 PCI_MASTER_ENABLE (1, SELF);
147
148 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
149 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
150 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
151 (1 << 18);
152 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
153 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
154
155 /* ronen:
156 * add write to pci remap registers for 64460.
157 * in 64360 when writing to pci base go and overide remap automaticaly,
158 * in 64460 it doesn't
159 */
160 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
161 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
162 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
163
164 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
165 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
166 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
167
168 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
169 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
170 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
171
172 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
173 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
174 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
175
176 /* PCI interface settings */
177 /* Timeout set to retry forever */
178 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
179 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
180
181 /* ronen - enable only CS0 and Internal reg!! */
182 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
183 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
184
185 /* ronen:
186 * update the pci internal registers base address.
187 */
188 #ifdef MAP_PCI
189 for (stat = 0; stat <= PCI_HOST1; stat++)
190 pciWriteConfigReg (stat,
191 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
192 SELF, CONFIG_SYS_GT_REGS);
193 #endif
194
195 }
196 #endif
197
198 /* Setup CPU interface paramaters */
199 static void gt_cpu_config (void)
200 {
201 cpu_t cpu = get_cpu_type ();
202 ulong tmp;
203
204 /* cpu configuration register */
205 tmp = GTREGREAD (CPU_CONFIGURATION);
206 /* set the SINGLE_CPU bit see MV64460 */
207 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
208 tmp |= CPU_CONF_SINGLE_CPU;
209 #endif
210 tmp &= ~CPU_CONF_AACK_DELAY_2;
211 tmp |= CPU_CONF_DP_VALID;
212 tmp |= CPU_CONF_AP_VALID;
213 tmp |= CPU_CONF_PIPELINE;
214 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
215
216 /* CPU master control register */
217 tmp = GTREGREAD (CPU_MASTER_CONTROL);
218 tmp |= CPU_MAST_CTL_ARB_EN;
219
220 if ((cpu == CPU_7400) ||
221 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
222
223 tmp |= CPU_MAST_CTL_CLEAN_BLK;
224 tmp |= CPU_MAST_CTL_FLUSH_BLK;
225
226 } else {
227 /* cleanblock must be cleared for CPUs
228 * that do not support this command (603e, 750)
229 * see Res#1 */
230 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
231 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
232 }
233 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
234 }
235
236 /*
237 * board_early_init_f.
238 *
239 * set up gal. device mappings, etc.
240 */
241 int board_early_init_f (void)
242 {
243 /* set up the GT the way the kernel wants it
244 * the call to move the GT register space will obviously
245 * fail if it has already been done, but we're going to assume
246 * that if it's not at the power-on location, it's where we put
247 * it last time. (huber)
248 */
249 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
250
251 #ifdef CONFIG_PCI
252 gt_pci_config ();
253 #endif
254 /* mask all external interrupt sources */
255 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
256 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
257 /* new in >MV6436x */
258 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
259 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
260 /* --------------------- */
261 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
262 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
263 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
264 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
265
266 /* Device and Boot bus settings
267 */
268 memoryMapDeviceSpace(DEVICE0, 0, 0);
269 GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
270 memoryMapDeviceSpace(DEVICE1, 0, 0);
271 GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
272 memoryMapDeviceSpace(DEVICE2, 0, 0);
273 GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
274 memoryMapDeviceSpace(DEVICE3, 0, 0);
275 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
276
277 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
278
279 gt_cpu_config();
280
281 /* MPP setup */
282 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
283 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
284 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
285 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
286
287 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
288
289 set_led(LED_RED);
290
291 return 0;
292 }
293
294 /* various things to do after relocation */
295
296 int misc_init_r ()
297 {
298 u8 val;
299
300 icache_enable ();
301 #ifdef CONFIG_SYS_L2
302 l2cache_enable ();
303 #endif
304 #ifdef CONFIG_MPSC
305 mpsc_sdma_init ();
306 mpsc_init2 ();
307 #endif
308
309 /*
310 * Enable trickle changing in RTC upon powerup
311 * No diode, 250 ohm series resistor
312 */
313 val = 0xa5;
314 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
315
316 return 0;
317 }
318
319 void after_reloc (ulong dest_addr, gd_t * gd)
320 {
321 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
322
323 /* display_mem_map(); */
324
325 /* now, jump to the main U-Boot board init code */
326 set_led(LED_GREEN);
327 board_init_r (gd, dest_addr);
328 /* NOTREACHED */
329 }
330
331 /*
332 * Check Board Identity:
333 * right now, assume borad type. (there is just one...after all)
334 */
335
336 int checkboard (void)
337 {
338 char *s = getenv("serial#");
339
340 printf("Board: %s", CONFIG_SYS_BOARD_NAME);
341
342 if (s != NULL) {
343 puts(", serial# ");
344 puts(s);
345 }
346 putc('\n');
347
348 return (0);
349 }
350
351 void set_led(int col)
352 {
353 int tmp;
354 int on_pin;
355 int off_pin;
356
357 /* Program Mpp[22] as Gpp[22]
358 * Program Mpp[23] as Gpp[23]
359 */
360 tmp = GTREGREAD(MPP_CONTROL2);
361 tmp &= 0x00ffffff;
362 GT_REG_WRITE(MPP_CONTROL2,tmp);
363
364 /* Program Gpp[22] and Gpp[23] as output
365 */
366 tmp = GTREGREAD(GPP_IO_CONTROL);
367 tmp |= 0x00C00000;
368 GT_REG_WRITE(GPP_IO_CONTROL, tmp);
369
370 /* Program Gpp[22] and Gpp[23] as active high
371 */
372 tmp = GTREGREAD(GPP_LEVEL_CONTROL);
373 tmp &= 0xff3fffff;
374 GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
375
376 switch(col) {
377 default:
378 case LED_OFF :
379 on_pin = 0;
380 off_pin = ((1 << 23) | (1 << 22));
381 break;
382 case LED_RED :
383 on_pin = (1 << 23);
384 off_pin = (1 << 22);
385 break;
386 case LED_GREEN :
387 on_pin = (1 << 22);
388 off_pin = (1 << 23);
389 break;
390 case LED_ORANGE :
391 on_pin = ((1 << 23) | (1 << 22));
392 off_pin = 0;
393 break;
394 }
395
396 /* Set output Gpp[22] and Gpp[23]
397 */
398 tmp = GTREGREAD(GPP_VALUE);
399 tmp |= on_pin;
400 tmp &= ~off_pin;
401 GT_REG_WRITE(GPP_VALUE, tmp);
402 }
403
404 int display_mem_map (void)
405 {
406 int i;
407 unsigned int base, size, width;
408 #ifdef CONFIG_PCI
409 int j;
410 #endif
411
412 /* SDRAM */
413 printf ("SD (DDR) RAM\n");
414 for (i = 0; i <= BANK3; i++) {
415 base = memoryGetBankBaseAddress (i);
416 size = memoryGetBankSize (i);
417 if (size != 0)
418 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
419 i, base, size >> 20);
420 }
421 #ifdef CONFIG_PCI
422 /* CPU's PCI windows */
423 for (i = 0; i <= PCI_HOST1; i++) {
424 printf ("\nCPU's PCI %d windows\n", i);
425 base = pciGetSpaceBase (i, PCI_IO);
426 size = pciGetSpaceSize (i, PCI_IO);
427 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
428 size >> 20);
429 /* ronen currently only first PCI MEM is used 3 */
430 for (j = 0; j <= PCI_REGION0; j++) {
431 base = pciGetSpaceBase (i, j);
432 size = pciGetSpaceSize (i, j);
433 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
434 j, base, size >> 20);
435 }
436 }
437 #endif /* of CONFIG_PCI */
438
439 /* Bootrom */
440 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
441 size = memoryGetDeviceSize (BOOT_DEVICE);
442 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
443 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
444 base, size >> 20, width);
445
446 return (0);
447 }
448
449 /* DRAM check routines copied from gw8260 */
450
451 #if defined (CONFIG_SYS_DRAM_TEST)
452
453 /*********************************************************************/
454 /* NAME: move64() - moves a double word (64-bit) */
455 /* */
456 /* DESCRIPTION: */
457 /* this function performs a double word move from the data at */
458 /* the source pointer to the location at the destination pointer. */
459 /* */
460 /* INPUTS: */
461 /* unsigned long long *src - pointer to data to move */
462 /* */
463 /* OUTPUTS: */
464 /* unsigned long long *dest - pointer to locate to move data */
465 /* */
466 /* RETURNS: */
467 /* None */
468 /* */
469 /* RESTRICTIONS/LIMITATIONS: */
470 /* May cloober fr0. */
471 /* */
472 /*********************************************************************/
473 static void move64 (unsigned long long *src, unsigned long long *dest)
474 {
475 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
476 "stfd 0, 0(4)" /* *dest = fpr0 */
477 : : : "fr0"); /* Clobbers fr0 */
478 return;
479 }
480
481
482 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
483
484 unsigned long long pattern[] = {
485 0xaaaaaaaaaaaaaaaaULL,
486 0xccccccccccccccccULL,
487 0xf0f0f0f0f0f0f0f0ULL,
488 0xff00ff00ff00ff00ULL,
489 0xffff0000ffff0000ULL,
490 0xffffffff00000000ULL,
491 0x00000000ffffffffULL,
492 0x0000ffff0000ffffULL,
493 0x00ff00ff00ff00ffULL,
494 0x0f0f0f0f0f0f0f0fULL,
495 0x3333333333333333ULL,
496 0x5555555555555555ULL
497 };
498
499 /*********************************************************************/
500 /* NAME: mem_test_data() - test data lines for shorts and opens */
501 /* */
502 /* DESCRIPTION: */
503 /* Tests data lines for shorts and opens by forcing adjacent data */
504 /* to opposite states. Because the data lines could be routed in */
505 /* an arbitrary manner the must ensure test patterns ensure that */
506 /* every case is tested. By using the following series of binary */
507 /* patterns every combination of adjacent bits is test regardless */
508 /* of routing. */
509 /* */
510 /* ...101010101010101010101010 */
511 /* ...110011001100110011001100 */
512 /* ...111100001111000011110000 */
513 /* ...111111110000000011111111 */
514 /* */
515 /* Carrying this out, gives us six hex patterns as follows: */
516 /* */
517 /* 0xaaaaaaaaaaaaaaaa */
518 /* 0xcccccccccccccccc */
519 /* 0xf0f0f0f0f0f0f0f0 */
520 /* 0xff00ff00ff00ff00 */
521 /* 0xffff0000ffff0000 */
522 /* 0xffffffff00000000 */
523 /* */
524 /* The number test patterns will always be given by: */
525 /* */
526 /* log(base 2)(number data bits) = log2 (64) = 6 */
527 /* */
528 /* To test for short and opens to other signals on our boards. we */
529 /* simply */
530 /* test with the 1's complemnt of the paterns as well. */
531 /* */
532 /* OUTPUTS: */
533 /* Displays failing test pattern */
534 /* */
535 /* RETURNS: */
536 /* 0 - Passed test */
537 /* 1 - Failed test */
538 /* */
539 /* RESTRICTIONS/LIMITATIONS: */
540 /* Assumes only one one SDRAM bank */
541 /* */
542 /*********************************************************************/
543 int mem_test_data (void)
544 {
545 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
546 unsigned long long temp64 = 0;
547 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
548 int i;
549 unsigned int hi, lo;
550
551 for (i = 0; i < num_patterns; i++) {
552 move64 (&(pattern[i]), pmem);
553 move64 (pmem, &temp64);
554
555 /* hi = (temp64>>32) & 0xffffffff; */
556 /* lo = temp64 & 0xffffffff; */
557 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
558
559 hi = (pattern[i] >> 32) & 0xffffffff;
560 lo = pattern[i] & 0xffffffff;
561 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
562
563 if (temp64 != pattern[i]) {
564 printf ("\n Data Test Failed, pattern 0x%08x%08x",
565 hi, lo);
566 return 1;
567 }
568 }
569
570 return 0;
571 }
572 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
573
574 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
575 /*********************************************************************/
576 /* NAME: mem_test_address() - test address lines */
577 /* */
578 /* DESCRIPTION: */
579 /* This function performs a test to verify that each word im */
580 /* memory is uniquly addressable. The test sequence is as follows: */
581 /* */
582 /* 1) write the address of each word to each word. */
583 /* 2) verify that each location equals its address */
584 /* */
585 /* OUTPUTS: */
586 /* Displays failing test pattern and address */
587 /* */
588 /* RETURNS: */
589 /* 0 - Passed test */
590 /* 1 - Failed test */
591 /* */
592 /* RESTRICTIONS/LIMITATIONS: */
593 /* */
594 /* */
595 /*********************************************************************/
596 int mem_test_address (void)
597 {
598 volatile unsigned int *pmem =
599 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
600 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
601 unsigned int i;
602
603 /* write address to each location */
604 for (i = 0; i < size; i++)
605 pmem[i] = i;
606
607 /* verify each loaction */
608 for (i = 0; i < size; i++) {
609 if (pmem[i] != i) {
610 printf ("\n Address Test Failed at 0x%x", i);
611 return 1;
612 }
613 }
614 return 0;
615 }
616 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
617
618 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
619 /*********************************************************************/
620 /* NAME: mem_march() - memory march */
621 /* */
622 /* DESCRIPTION: */
623 /* Marches up through memory. At each location verifies rmask if */
624 /* read = 1. At each location write wmask if write = 1. Displays */
625 /* failing address and pattern. */
626 /* */
627 /* INPUTS: */
628 /* volatile unsigned long long * base - start address of test */
629 /* unsigned int size - number of dwords(64-bit) to test */
630 /* unsigned long long rmask - read verify mask */
631 /* unsigned long long wmask - wrtie verify mask */
632 /* short read - verifies rmask if read = 1 */
633 /* short write - writes wmask if write = 1 */
634 /* */
635 /* OUTPUTS: */
636 /* Displays failing test pattern and address */
637 /* */
638 /* RETURNS: */
639 /* 0 - Passed test */
640 /* 1 - Failed test */
641 /* */
642 /* RESTRICTIONS/LIMITATIONS: */
643 /* */
644 /* */
645 /*********************************************************************/
646 int mem_march (volatile unsigned long long *base,
647 unsigned int size,
648 unsigned long long rmask,
649 unsigned long long wmask, short read, short write)
650 {
651 unsigned int i;
652 unsigned long long temp = 0;
653 unsigned int hitemp, lotemp, himask, lomask;
654
655 for (i = 0; i < size; i++) {
656 if (read != 0) {
657 /* temp = base[i]; */
658 move64 ((unsigned long long *) &(base[i]), &temp);
659 if (rmask != temp) {
660 hitemp = (temp >> 32) & 0xffffffff;
661 lotemp = temp & 0xffffffff;
662 himask = (rmask >> 32) & 0xffffffff;
663 lomask = rmask & 0xffffffff;
664
665 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
666 return 1;
667 }
668 }
669 if (write != 0) {
670 /* base[i] = wmask; */
671 move64 (&wmask, (unsigned long long *) &(base[i]));
672 }
673 }
674 return 0;
675 }
676 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
677
678 /*********************************************************************/
679 /* NAME: mem_test_walk() - a simple walking ones test */
680 /* */
681 /* DESCRIPTION: */
682 /* Performs a walking ones through entire physical memory. The */
683 /* test uses as series of memory marches, mem_march(), to verify */
684 /* and write the test patterns to memory. The test sequence is as */
685 /* follows: */
686 /* 1) march writing 0000...0001 */
687 /* 2) march verifying 0000...0001 , writing 0000...0010 */
688 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
689 /* the write mask equals 1000...0000 */
690 /* 4) march verifying 1000...0000 */
691 /* The test fails if any of the memory marches return a failure. */
692 /* */
693 /* OUTPUTS: */
694 /* Displays which pass on the memory test is executing */
695 /* */
696 /* RETURNS: */
697 /* 0 - Passed test */
698 /* 1 - Failed test */
699 /* */
700 /* RESTRICTIONS/LIMITATIONS: */
701 /* */
702 /* */
703 /*********************************************************************/
704 int mem_test_walk (void)
705 {
706 unsigned long long mask;
707 volatile unsigned long long *pmem =
708 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
709 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
710
711 unsigned int i;
712
713 mask = 0x01;
714
715 printf ("Initial Pass");
716 mem_march (pmem, size, 0x0, 0x1, 0, 1);
717
718 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
719 printf (" ");
720 printf (" ");
721 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
722
723 for (i = 0; i < 63; i++) {
724 printf ("Pass %2d", i + 2);
725 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
726 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
727 return 1;
728 }
729 mask = mask << 1;
730 printf ("\b\b\b\b\b\b\b");
731 }
732
733 printf ("Last Pass");
734 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
735 /* printf("mask: 0x%x", mask); */
736 return 1;
737 }
738 printf ("\b\b\b\b\b\b\b\b\b");
739 printf (" ");
740 printf ("\b\b\b\b\b\b\b\b\b");
741
742 return 0;
743 }
744
745 /*********************************************************************/
746 /* NAME: testdram() - calls any enabled memory tests */
747 /* */
748 /* DESCRIPTION: */
749 /* Runs memory tests if the environment test variables are set to */
750 /* 'y'. */
751 /* */
752 /* INPUTS: */
753 /* testdramdata - If set to 'y', data test is run. */
754 /* testdramaddress - If set to 'y', address test is run. */
755 /* testdramwalk - If set to 'y', walking ones test is run */
756 /* */
757 /* OUTPUTS: */
758 /* None */
759 /* */
760 /* RETURNS: */
761 /* 0 - Passed test */
762 /* 1 - Failed test */
763 /* */
764 /* RESTRICTIONS/LIMITATIONS: */
765 /* */
766 /* */
767 /*********************************************************************/
768 int testdram (void)
769 {
770 char *s;
771 int rundata = 0;
772 int runaddress = 0;
773 int runwalk = 0;
774
775 #ifdef CONFIG_SYS_DRAM_TEST_DATA
776 s = getenv ("testdramdata");
777 rundata = (s && (*s == 'y')) ? 1 : 0;
778 #endif
779 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
780 s = getenv ("testdramaddress");
781 runaddress = (s && (*s == 'y')) ? 1 : 0;
782 #endif
783 #ifdef CONFIG_SYS_DRAM_TEST_WALK
784 s = getenv ("testdramwalk");
785 runwalk = (s && (*s == 'y')) ? 1 : 0;
786 #endif
787
788 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
789 printf ("Testing RAM from 0x%08x to 0x%08x ... "
790 "(don't panic... that will take a moment !!!!)\n",
791 CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
792 #ifdef CONFIG_SYS_DRAM_TEST_DATA
793 if (rundata == 1) {
794 printf ("Test DATA ... ");
795 if (mem_test_data () == 1) {
796 printf ("failed \n");
797 return 1;
798 } else
799 printf ("ok \n");
800 }
801 #endif
802 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
803 if (runaddress == 1) {
804 printf ("Test ADDRESS ... ");
805 if (mem_test_address () == 1) {
806 printf ("failed \n");
807 return 1;
808 } else
809 printf ("ok \n");
810 }
811 #endif
812 #ifdef CONFIG_SYS_DRAM_TEST_WALK
813 if (runwalk == 1) {
814 printf ("Test WALKING ONEs ... ");
815 if (mem_test_walk () == 1) {
816 printf ("failed \n");
817 return 1;
818 } else
819 printf ("ok \n");
820 }
821 #endif
822 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
823 printf ("passed\n");
824 return 0;
825
826 }
827 #endif /* CONFIG_SYS_DRAM_TEST */
828
829 /* ronen - the below functions are used by the bootm function */
830 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
831 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
832 /* the kernel data areas. */
833 /* - we diable and invalidate the icache and dcache. */
834 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
835 {
836 u32 temp;
837
838 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
839 if ((temp & 0xffff) == new_loc >> 16)
840 return;
841
842 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
843 0xffff0000) | (new_loc >> 16);
844
845 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
846
847 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
848 new_loc |
849 (INTERNAL_SPACE_DECODE)))))
850 != temp);
851
852 }
"Das U-Boot" Source Tree