]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/prodrive/pdnb3/nand.c
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
30 struct pdnb3_ndfc_regs
{
39 static struct pdnb3_ndfc_regs
*pdnb3_ndfc
;
41 #define readb(addr) *(volatile u_char *)(addr)
42 #define readl(addr) *(volatile u_long *)(addr)
43 #define writeb(d,addr) *(volatile u_char *)(addr) = (d)
46 * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
47 * the NAND devices. The NDFC has command, address and data registers that
48 * when accessed will set up the NAND flash pins appropriately. We'll use the
49 * hwcontrol function to save the configuration in a global variable.
50 * We can then use this information in the read and write functions to
51 * determine which NDFC register to access.
53 * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
55 static void pdnb3_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
)
75 writeb(0x00, &(pdnb3_ndfc
->term
));
80 static void pdnb3_nand_write_byte(struct mtd_info
*mtd
, u_char byte
)
83 writeb(byte
, &(pdnb3_ndfc
->cmd
));
85 writeb(byte
, &(pdnb3_ndfc
->addr
));
87 writeb(byte
, &(pdnb3_ndfc
->data
));
90 static u_char
pdnb3_nand_read_byte(struct mtd_info
*mtd
)
92 return readb(&(pdnb3_ndfc
->data
));
95 static void pdnb3_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
99 for (i
= 0; i
< len
; i
++) {
101 writeb(buf
[i
], &(pdnb3_ndfc
->cmd
));
102 else if (hwctl
& 0x2)
103 writeb(buf
[i
], &(pdnb3_ndfc
->addr
));
105 writeb(buf
[i
], &(pdnb3_ndfc
->data
));
109 static void pdnb3_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
114 for (i
= 0; i
< len
; i
++)
115 buf
[i
] = readb(&(pdnb3_ndfc
->data
));
117 ulong
*ptr
= (ulong
*)buf
;
118 int count
= len
>> 2;
120 for (i
= 0; i
< count
; i
++)
121 *ptr
++ = readl(&(pdnb3_ndfc
->data
));
125 static int pdnb3_nand_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
129 for (i
= 0; i
< len
; i
++)
130 if (buf
[i
] != readb(&(pdnb3_ndfc
->data
)))
136 static int pdnb3_nand_dev_ready(struct mtd_info
*mtd
)
141 * Blocking read to wait for NAND to be ready
143 val
= readb(&(pdnb3_ndfc
->wait
));
151 void board_nand_init(struct nand_chip
*nand
)
153 pdnb3_ndfc
= (struct pdnb3_ndfc_regs
*)CFG_NAND_BASE
;
155 nand
->eccmode
= NAND_ECC_SOFT
;
157 /* Set address of NAND IO lines (Using Linear Data Access Region) */
158 nand
->IO_ADDR_R
= (void __iomem
*) ((ulong
) pdnb3_ndfc
+ 0x4);
159 nand
->IO_ADDR_W
= (void __iomem
*) ((ulong
) pdnb3_ndfc
+ 0x4);
160 /* Reference hardware control function */
161 nand
->hwcontrol
= pdnb3_nand_hwcontrol
;
162 /* Set command delay time */
163 nand
->hwcontrol
= pdnb3_nand_hwcontrol
;
164 nand
->write_byte
= pdnb3_nand_write_byte
;
165 nand
->read_byte
= pdnb3_nand_read_byte
;
166 nand
->write_buf
= pdnb3_nand_write_buf
;
167 nand
->read_buf
= pdnb3_nand_read_buf
;
168 nand
->verify_buf
= pdnb3_nand_verify_buf
;
169 nand
->dev_ready
= pdnb3_nand_dev_ready
;