board/rbc823/rbc823.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include "mpc8xx.h"
  26 #include <linux/mtd/doc2000.h>
  27
  28 extern int kbd_init(void);
  29 extern int drv_kbd_init(void);
  30
  31 /* ------------------------------------------------------------------------- */
  32
  33 static long int dram_size (long int, long int *, long int);
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 #define _NOT_USED_      0xFFFFFFFF
  38
  39 const uint sdram_table[] =
  40 {
  41         /*
  42          * Single Read. (Offset 0 in UPMA RAM)
  43          */
  44         0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  45         0x1FF77C47, /* last */
  46         /*
  47          * SDRAM Initialization (offset 5 in UPMA RAM)
  48          *
  49          * This is no UPM entry point. The following definition uses
  50          * the remaining space to establish an initialization
  51          * sequence, which is executed by a RUN command.
  52          *
  53          */
  54                     0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
  55         /*
  56          * Burst Read. (Offset 8 in UPMA RAM)
  57          */
  58         0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  59         0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  60         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  61         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  62         /*
  63          * Single Write. (Offset 18 in UPMA RAM)
  64          */
  65         0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  66         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  67         /*
  68          * Burst Write. (Offset 20 in UPMA RAM)
  69          */
  70         0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  71         0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
  72                                             _NOT_USED_,
  73         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  74         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  75         /*
  76          * Refresh  (Offset 30 in UPMA RAM)
  77          */
  78         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  79         0xFFFFFC84, 0xFFFFFC07, /* last */
  80                                 _NOT_USED_, _NOT_USED_,
  81         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82         /*
  83          * Exception. (Offset 3c in UPMA RAM)
  84          */
  85         0x1FF7FC07, /* last */
  86                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87 };
  88
  89 const uint static_table[] =
  90 {
  91         /*
  92          * Single Read. (Offset 0 in UPMA RAM)
  93          */
  94         0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
  95         0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
  96         0xFFFFFC04, 0xFFFFFC05, /* last */
  97                                 _NOT_USED_, _NOT_USED_,
  98         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  99         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 100         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 101         /*
 102          * Single Write. (Offset 18 in UPMA RAM)
 103          */
 104         0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
 105         0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
 106         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 107         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 108         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 109         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 110         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 111         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 112         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 113         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 114 };
 115
 116 /* ------------------------------------------------------------------------- */
 117
 118 /*
 119  * Check Board Identity:
 120  *
 121  * Test TQ ID string (TQM8xx...)
 122  * If present, check for "L" type (no second DRAM bank),
 123  * otherwise "L" type is assumed as default.
 124  *
 125  * Return 1 for "L" type, 0 else.
 126  */
 127
 128 int checkboard (void)
 129 {
 130         char buf[64];
 131         int i = getenv_f("serial#", buf, sizeof(buf));
 132
 133         if (i < 0 || strncmp(buf, "TQM8", 4)) {
 134                 printf ("### No HW ID - assuming RBC823\n");
 135                 return (0);
 136         }
 137
 138         puts(buf);
 139         putc('\n');
 140
 141         return (0);
 142 }
 143
 144 /* ------------------------------------------------------------------------- */
 145
 146 phys_size_t initdram (int board_type)
 147 {
 148         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 149         volatile memctl8xx_t *memctl = &immap->im_memctl;
 150         long int size_b0, size8, size9;
 151
 152         upmconfig (UPMA, (uint *) sdram_table,
 153                    sizeof (sdram_table) / sizeof (uint));
 154
 155         /*
 156          * 1 Bank of 64Mbit x 2 devices
 157          */
 158         memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 159         memctl->memc_mar = 0x00000088;
 160
 161         /*
 162          * Map controller SDRAM bank 0
 163          */
 164         memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 165         memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 166         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 167         udelay (200);
 168
 169         /*
 170          * Perform SDRAM initializsation sequence
 171          */
 172         memctl->memc_mcr = 0x80008105;  /* SDRAM bank 0 */
 173         udelay (1);
 174         memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
 175         udelay (200);
 176         memctl->memc_mcr = 0x80008130;  /* SDRAM bank 0 - execute twice */
 177         udelay (1);
 178         memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
 179         udelay (200);
 180
 181         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 182         udelay (1000);
 183
 184         /*
 185          * Preliminary prescaler for refresh (depends on number of
 186          * banks): This value is selected for four cycles every 62.4 us
 187          * with two SDRAM banks or four cycles every 31.2 us with one
 188          * bank. It will be adjusted after memory sizing.
 189          */
 190         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;   /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
 191
 192         /*
 193          * Check Bank 0 Memory Size for re-configuration
 194          *
 195          * try 8 column mode
 196          */
 197         size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
 198                            SDRAM_MAX_SIZE);
 199         udelay (1000);
 200
 201         /*
 202          * try 9 column mode
 203          */
 204         size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
 205                            SDRAM_MAX_SIZE);
 206
 207         if (size8 < size9) {    /* leave configuration at 9 columns     */
 208                 size_b0 = size9;
 209 /*      debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
 210         } else {                /* back to 8 columns                    */
 211                 size_b0 = size8;
 212                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 213                 udelay (500);
 214 /*      debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
 215         }
 216
 217         udelay (1000);
 218
 219         /*
 220          * Adjust refresh rate depending on SDRAM type, both banks
 221          * For types > 128 MBit leave it at the current (fast) rate
 222          */
 223         if ((size_b0 < 0x02000000)) {
 224                 /* reduce to 15.6 us (62.4 us / quad) */
 225                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 226                 udelay (1000);
 227         }
 228
 229         /* SDRAM Bank 0 is bigger - map first       */
 230
 231         memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 232         memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 233
 234         udelay (10000);
 235
 236         return (size_b0);
 237 }
 238
 239 /* ------------------------------------------------------------------------- */
 240
 241 /*
 242  * Check memory range for valid RAM. A simple memory test determines
 243  * the actually available RAM size between addresses `base' and
 244  * `base + maxsize'. Some (not all) hardware errors are detected:
 245  * - short between address lines
 246  * - short between data lines
 247  */
 248
 249 static long int dram_size (long int mamr_value, long int *base,
 250                            long int maxsize)
 251 {
 252         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 253         volatile memctl8xx_t *memctl = &immap->im_memctl;
 254
 255         memctl->memc_mamr = mamr_value;
 256
 257         return (get_ram_size (base, maxsize));
 258 }
 259
 260 #ifdef CONFIG_CMD_DOC
 261 void doc_init (void)
 262 {
 263         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 264         volatile memctl8xx_t *memctl = &immap->im_memctl;
 265
 266         upmconfig (UPMB, (uint *) static_table,
 267                    sizeof (static_table) / sizeof (uint));
 268         memctl->memc_mbmr = MAMR_DSA_1_CYCL;
 269
 270         doc_probe (FLASH_BASE1_PRELIM);
 271 }
 272 #endif