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ARM: Rmobile: Rename CONFIG_RMOBILE to CONFIG_ARCH_RMOBILE
[people/ms/u-boot.git] / board / renesas / alt / alt.c
1 /*
2 * board/renesas/alt/alt.c
3 *
4 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9 #include <common.h>
10 #include <malloc.h>
11 #include <dm.h>
12 #include <dm/platform_data/serial_sh.h>
13 #include <asm/processor.h>
14 #include <asm/mach-types.h>
15 #include <asm/io.h>
16 #include <asm/errno.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/gpio.h>
19 #include <asm/arch/rmobile.h>
20 #include <asm/arch/rcar-mstp.h>
21 #include <asm/arch/mmc.h>
22 #include <asm/arch/sh_sdhi.h>
23 #include <netdev.h>
24 #include <miiphy.h>
25 #include <i2c.h>
26 #include <div64.h>
27 #include "qos.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #define CLK2MHZ(clk) (clk / 1000 / 1000)
32 void s_init(void)
33 {
34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
36
37 /* Watchdog init */
38 writel(0xA5A5A500, &rwdt->rwtcsra);
39 writel(0xA5A5A500, &swdt->swtcsra);
40
41 /* QoS */
42 qos_init();
43 }
44
45 #define TMU0_MSTP125 (1 << 25)
46 #define SCIF2_MSTP719 (1 << 19)
47 #define ETHER_MSTP813 (1 << 13)
48 #define IIC1_MSTP323 (1 << 23)
49 #define MMC0_MSTP315 (1 << 15)
50 #define SDHI0_MSTP314 (1 << 14)
51 #define SDHI1_MSTP312 (1 << 12)
52
53 #define SD1CKCR 0xE6150078
54 #define SD1_97500KHZ 0x7
55
56 int board_early_init_f(void)
57 {
58 /* TMU */
59 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
60
61 /* SCIF2 */
62 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
63
64 /* ETHER */
65 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
66
67 /* IIC1 / sh-i2c ch1 */
68 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
69
70 #ifdef CONFIG_SH_MMCIF
71 /* MMC */
72 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
73 #endif
74
75 #ifdef CONFIG_SH_SDHI
76 /* SDHI0, 1 */
77 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
78
79 /*
80 * SD0 clock is set to 97.5MHz by default.
81 * Set SD1 to the 97.5MHz as well.
82 */
83 writel(SD1_97500KHZ, SD1CKCR);
84 #endif
85 return 0;
86 }
87
88 int board_init(void)
89 {
90 /* adress of boot parameters */
91 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
92
93 /* Init PFC controller */
94 r8a7794_pinmux_init();
95
96 /* Ether Enable */
97 #if defined(CONFIG_R8A7794_ETHERNET_B)
98 gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
99 gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
100 gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
101 gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
102 gpio_request(GPIO_FN_ETH_LINK_B, NULL);
103 gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
104 gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
105 gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
106 gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
107 gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
108 gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
109 gpio_request(GPIO_FN_ETH_MDC_B, NULL);
110 #else
111 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
112 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
113 gpio_request(GPIO_FN_ETH_RXD0, NULL);
114 gpio_request(GPIO_FN_ETH_RXD1, NULL);
115 gpio_request(GPIO_FN_ETH_LINK, NULL);
116 gpio_request(GPIO_FN_ETH_REFCLK, NULL);
117 gpio_request(GPIO_FN_ETH_MDIO, NULL);
118 gpio_request(GPIO_FN_ETH_TXD1, NULL);
119 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
120 gpio_request(GPIO_FN_ETH_MAGIC, NULL);
121 gpio_request(GPIO_FN_ETH_TXD0, NULL);
122 gpio_request(GPIO_FN_ETH_MDC, NULL);
123 #endif
124 gpio_request(GPIO_FN_IRQ8, NULL);
125
126 /* PHY reset */
127 gpio_request(GPIO_GP_1_24, NULL);
128 gpio_direction_output(GPIO_GP_1_24, 0);
129 mdelay(20);
130 gpio_set_value(GPIO_GP_1_24, 1);
131 udelay(1);
132
133 return 0;
134 }
135
136 #define CXR24 0xEE7003C0 /* MAC address high register */
137 #define CXR25 0xEE7003C8 /* MAC address low register */
138 int board_eth_init(bd_t *bis)
139 {
140 #ifdef CONFIG_SH_ETHER
141 int ret = -ENODEV;
142 u32 val;
143 unsigned char enetaddr[6];
144
145 ret = sh_eth_initialize(bis);
146 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
147 return ret;
148
149 /* Set Mac address */
150 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
151 enetaddr[2] << 8 | enetaddr[3];
152 writel(val, CXR24);
153
154 val = enetaddr[4] << 8 | enetaddr[5];
155 writel(val, CXR25);
156
157 return ret;
158 #else
159 return 0;
160 #endif
161 }
162
163 int board_mmc_init(bd_t *bis)
164 {
165 int ret = -ENODEV;
166
167 #ifdef CONFIG_SH_MMCIF
168 gpio_request(GPIO_GP_4_31, NULL);
169 gpio_set_value(GPIO_GP_4_31, 1);
170
171 ret = mmcif_mmc_init();
172 #endif
173
174 #ifdef CONFIG_SH_SDHI
175 gpio_request(GPIO_FN_SD0_DATA0, NULL);
176 gpio_request(GPIO_FN_SD0_DATA1, NULL);
177 gpio_request(GPIO_FN_SD0_DATA2, NULL);
178 gpio_request(GPIO_FN_SD0_DATA3, NULL);
179 gpio_request(GPIO_FN_SD0_CLK, NULL);
180 gpio_request(GPIO_FN_SD0_CMD, NULL);
181 gpio_request(GPIO_FN_SD0_CD, NULL);
182 gpio_request(GPIO_FN_SD1_DATA0, NULL);
183 gpio_request(GPIO_FN_SD1_DATA1, NULL);
184 gpio_request(GPIO_FN_SD1_DATA2, NULL);
185 gpio_request(GPIO_FN_SD1_DATA3, NULL);
186 gpio_request(GPIO_FN_SD1_CLK, NULL);
187 gpio_request(GPIO_FN_SD1_CMD, NULL);
188 gpio_request(GPIO_FN_SD1_CD, NULL);
189
190 /* SDHI 0 */
191 gpio_request(GPIO_GP_2_26, NULL);
192 gpio_request(GPIO_GP_2_29, NULL);
193 gpio_direction_output(GPIO_GP_2_26, 1);
194 gpio_direction_output(GPIO_GP_2_29, 1);
195
196 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
197 SH_SDHI_QUIRK_16BIT_BUF);
198 if (ret)
199 return ret;
200
201 /* SDHI 1 */
202 gpio_request(GPIO_GP_4_26, NULL);
203 gpio_request(GPIO_GP_4_29, NULL);
204 gpio_direction_output(GPIO_GP_4_26, 1);
205 gpio_direction_output(GPIO_GP_4_29, 1);
206
207 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
208 #endif
209 return ret;
210 }
211
212 int dram_init(void)
213 {
214 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
215
216 return 0;
217 }
218
219 const struct rmobile_sysinfo sysinfo = {
220 CONFIG_ARCH_RMOBILE_BOARD_STRING
221 };
222
223 void reset_cpu(ulong addr)
224 {
225 u8 val;
226
227 i2c_set_bus_num(1); /* PowerIC connected to ch1 */
228 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
229 val |= 0x02;
230 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
231 }
232
233 static const struct sh_serial_platdata serial_platdata = {
234 .base = SCIF2_BASE,
235 .type = PORT_SCIF,
236 .clk = 14745600,
237 .clk_mode = EXT_CLK,
238 };
239
240 U_BOOT_DEVICE(alt_serials) = {
241 .name = "serial_sh",
242 .platdata = &serial_platdata,
243 };