board/renesas/alt/alt.c

   1 /*
   2  * board/renesas/alt/alt.c
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * SPDX-License-Identifier: GPL-2.0
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <dm.h>
  12 #include <dm/platform_data/serial_sh.h>
  13 #include <asm/processor.h>
  14 #include <asm/mach-types.h>
  15 #include <asm/io.h>
  16 #include <asm/errno.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/rmobile.h>
  20 #include <asm/arch/rcar-mstp.h>
  21 #include <asm/arch/mmc.h>
  22 #include <netdev.h>
  23 #include <miiphy.h>
  24 #include <i2c.h>
  25 #include <div64.h>
  26 #include "qos.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  31 void s_init(void)
  32 {
  33         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  34         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  35
  36         /* Watchdog init */
  37         writel(0xA5A5A500, &rwdt->rwtcsra);
  38         writel(0xA5A5A500, &swdt->swtcsra);
  39
  40         /* QoS */
  41         qos_init();
  42 }
  43
  44 #define TMU0_MSTP125    (1 << 25)
  45 #define SCIF2_MSTP719   (1 << 19)
  46 #define ETHER_MSTP813   (1 << 13)
  47 #define IIC1_MSTP323    (1 << 23)
  48 #define MMC0_MSTP315    (1 << 15)
  49
  50 int board_early_init_f(void)
  51 {
  52         /* TMU */
  53         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  54
  55         /* SCIF2 */
  56         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  57
  58         /* ETHER */
  59         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  60
  61         /* IIC1 / sh-i2c ch1 */
  62         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
  63
  64 #ifdef CONFIG_SH_MMCIF
  65         /* MMC */
  66         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
  67 #endif
  68         return 0;
  69 }
  70
  71 int board_init(void)
  72 {
  73         /* adress of boot parameters */
  74         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  75
  76         /* Init PFC controller */
  77         r8a7794_pinmux_init();
  78
  79         /* Ether Enable */
  80         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  81         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  82         gpio_request(GPIO_FN_ETH_RXD0, NULL);
  83         gpio_request(GPIO_FN_ETH_RXD1, NULL);
  84         gpio_request(GPIO_FN_ETH_LINK, NULL);
  85         gpio_request(GPIO_FN_ETH_REFCLK, NULL);
  86         gpio_request(GPIO_FN_ETH_MDIO, NULL);
  87         gpio_request(GPIO_FN_ETH_TXD1, NULL);
  88         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
  89         gpio_request(GPIO_FN_ETH_MAGIC, NULL);
  90         gpio_request(GPIO_FN_ETH_TXD0, NULL);
  91         gpio_request(GPIO_FN_ETH_MDC, NULL);
  92         gpio_request(GPIO_FN_IRQ8, NULL);
  93
  94         /* PHY reset */
  95         gpio_request(GPIO_GP_1_24, NULL);
  96         gpio_direction_output(GPIO_GP_1_24, 0);
  97         mdelay(20);
  98         gpio_set_value(GPIO_GP_1_24, 1);
  99         udelay(1);
 100
 101         return 0;
 102 }
 103
 104 #define CXR24 0xEE7003C0 /* MAC address high register */
 105 #define CXR25 0xEE7003C8 /* MAC address low register */
 106 int board_eth_init(bd_t *bis)
 107 {
 108 #ifdef CONFIG_SH_ETHER
 109         int ret = -ENODEV;
 110         u32 val;
 111         unsigned char enetaddr[6];
 112
 113         ret = sh_eth_initialize(bis);
 114         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 115                 return ret;
 116
 117         /* Set Mac address */
 118         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 119                 enetaddr[2] << 8 | enetaddr[3];
 120         writel(val, CXR24);
 121
 122         val = enetaddr[4] << 8 | enetaddr[5];
 123         writel(val, CXR25);
 124
 125         return ret;
 126 #else
 127         return 0;
 128 #endif
 129 }
 130
 131 int board_mmc_init(bd_t *bis)
 132 {
 133         int ret = 0;
 134
 135 #ifdef CONFIG_SH_MMCIF
 136         gpio_request(GPIO_GP_4_31, NULL);
 137         gpio_set_value(GPIO_GP_4_31, 1);
 138
 139         ret = mmcif_mmc_init();
 140 #endif
 141         return ret;
 142 }
 143
 144 int dram_init(void)
 145 {
 146         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 147
 148         return 0;
 149 }
 150
 151 const struct rmobile_sysinfo sysinfo = {
 152         CONFIG_RMOBILE_BOARD_STRING
 153 };
 154
 155 void reset_cpu(ulong addr)
 156 {
 157         u8 val;
 158
 159         i2c_set_bus_num(1); /* PowerIC connected to ch1 */
 160         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 161         val |= 0x02;
 162         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 163 }
 164
 165 static const struct sh_serial_platdata serial_platdata = {
 166         .base = SCIF2_BASE,
 167         .type = PORT_SCIF,
 168         .clk = 14745600,
 169         .clk_mode = EXT_CLK,
 170 };
 171
 172 U_BOOT_DEVICE(alt_serials) = {
 173         .name = "serial_sh",
 174         .platdata = &serial_platdata,
 175 };