board/renesas/alt/alt.c

   1 /*
   2  * board/renesas/alt/alt.c
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * SPDX-License-Identifier: GPL-2.0
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/processor.h>
  12 #include <asm/mach-types.h>
  13 #include <asm/io.h>
  14 #include <asm/errno.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/rmobile.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <i2c.h>
  21 #include <div64.h>
  22 #include "qos.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  27 void s_init(void)
  28 {
  29         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  30         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  31
  32         /* Watchdog init */
  33         writel(0xA5A5A500, &rwdt->rwtcsra);
  34         writel(0xA5A5A500, &swdt->swtcsra);
  35
  36         /* QoS */
  37         qos_init();
  38 }
  39
  40 #define MSTPSR1         0xE6150038
  41 #define SMSTPCR1        0xE6150134
  42 #define TMU0_MSTP125    (1 << 25)
  43
  44 #define MSTPSR7         0xE61501C4
  45 #define SMSTPCR7        0xE615014C
  46 #define SCIF2_MSTP719   (1 << 19)
  47
  48 #define MSTPSR8         0xE61509A0
  49 #define SMSTPCR8        0xE6150990
  50 #define ETHER_MSTP813   (1 << 13)
  51
  52 #define MSTPSR3         0xE6150048
  53 #define SMSTPCR3        0xE615013C
  54 #define IIC1_MSTP323    (1 << 23)
  55
  56 #define mstp_setbits(type, addr, saddr, set) \
  57         out_##type((saddr), in_##type(addr) | (set))
  58 #define mstp_clrbits(type, addr, saddr, clear) \
  59         out_##type((saddr), in_##type(addr) & ~(clear))
  60 #define mstp_setbits_le32(addr, saddr, set) \
  61         mstp_setbits(le32, addr, saddr, set)
  62 #define mstp_clrbits_le32(addr, saddr, clear)   \
  63         mstp_clrbits(le32, addr, saddr, clear)
  64
  65 int board_early_init_f(void)
  66 {
  67         /* TMU */
  68         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  69
  70         /* SCIF2 */
  71         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  72
  73         /* ETHER */
  74         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  75
  76         /* IIC1 / sh-i2c ch1 */
  77         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
  78
  79         return 0;
  80 }
  81
  82 void arch_preboot_os(void)
  83 {
  84         /* Disable TMU0 */
  85         mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  86 }
  87
  88 int board_init(void)
  89 {
  90         /* adress of boot parameters */
  91         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  92
  93         /* Init PFC controller */
  94         r8a7794_pinmux_init();
  95
  96         /* Ether Enable */
  97         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  98         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  99         gpio_request(GPIO_FN_ETH_RXD0, NULL);
 100         gpio_request(GPIO_FN_ETH_RXD1, NULL);
 101         gpio_request(GPIO_FN_ETH_LINK, NULL);
 102         gpio_request(GPIO_FN_ETH_REFCLK, NULL);
 103         gpio_request(GPIO_FN_ETH_MDIO, NULL);
 104         gpio_request(GPIO_FN_ETH_TXD1, NULL);
 105         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
 106         gpio_request(GPIO_FN_ETH_MAGIC, NULL);
 107         gpio_request(GPIO_FN_ETH_TXD0, NULL);
 108         gpio_request(GPIO_FN_ETH_MDC, NULL);
 109         gpio_request(GPIO_FN_IRQ8, NULL);
 110
 111         /* PHY reset */
 112         gpio_request(GPIO_GP_1_24, NULL);
 113         gpio_direction_output(GPIO_GP_1_24, 0);
 114         mdelay(20);
 115         gpio_set_value(GPIO_GP_1_24, 1);
 116         udelay(1);
 117
 118         return 0;
 119 }
 120
 121 #define CXR24 0xEE7003C0 /* MAC address high register */
 122 #define CXR25 0xEE7003C8 /* MAC address low register */
 123 int board_eth_init(bd_t *bis)
 124 {
 125 #ifdef CONFIG_SH_ETHER
 126         int ret = -ENODEV;
 127         u32 val;
 128         unsigned char enetaddr[6];
 129
 130         ret = sh_eth_initialize(bis);
 131         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 132                 return ret;
 133
 134         /* Set Mac address */
 135         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 136                 enetaddr[2] << 8 | enetaddr[3];
 137         writel(val, CXR24);
 138
 139         val = enetaddr[4] << 8 | enetaddr[5];
 140         writel(val, CXR25);
 141
 142         return ret;
 143 #else
 144         return 0;
 145 #endif
 146 }
 147
 148 int dram_init(void)
 149 {
 150         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 151
 152         return 0;
 153 }
 154
 155 const struct rmobile_sysinfo sysinfo = {
 156         CONFIG_RMOBILE_BOARD_STRING
 157 };
 158
 159 void reset_cpu(ulong addr)
 160 {
 161         u8 val;
 162
 163         i2c_set_bus_num(1); /* PowerIC connected to ch1 */
 164         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 165         val |= 0x02;
 166         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 167 }