board/renesas/ap325rxa/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Renesas Solutions Corp.
   3  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   4  *
   5  * board/ap325rxa/lowlevel_init.S
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <config.h>
  24 #include <version.h>
  25 #include <asm/processor.h>
  26 #include <asm/macro.h>
  27
  28 /*
  29  * Board specific low level init code, called _very_ early in the
  30  * startup sequence. Relocation to SDRAM has not happened yet, no
  31  * stack is available, bss section has not been initialised, etc.
  32  *
  33  * (Note: As no stack is available, no subroutines can be called...).
  34  */
  35
  36         .global lowlevel_init
  37
  38         .text
  39         .align  2
  40
  41 lowlevel_init:
  42         write16 DRVCRA_A, DRVCRA_D
  43
  44         write16 DRVCRB_A, DRVCRB_D
  45
  46         write16 RWTCSR_A, RWTCSR_D1
  47
  48         write16 RWTCNT_A, RWTCNT_D
  49
  50         write16 RWTCSR_A, RWTCSR_D2
  51
  52         write32 FRQCR_A, FRQCR_D
  53
  54         write32 CMNCR_A, CMNCR_D
  55
  56         write32 CS0BCR_A, CS0BCR_D
  57
  58         write32 CS4BCR_A, CS4BCR_D
  59
  60         write32 CS5ABCR_A, CS5ABCR_D
  61
  62         write32 CS5BBCR_A, CS5BBCR_D
  63
  64         write32 CS6ABCR_A, CS6ABCR_D
  65
  66         write32 CS6BBCR_A, CS6BBCR_D
  67
  68         write32 CS0WCR_A, CS0WCR_D
  69
  70         write32 CS4WCR_A, CS4WCR_D
  71
  72         write32 CS5AWCR_A, CS5AWCR_D
  73
  74         write32 CS5BWCR_A, CS5BWCR_D
  75
  76         write32 CS6AWCR_A, CS6AWCR_D
  77
  78         write32 CS6BWCR_A, CS6BWCR_D
  79
  80         write32 SBSC_SDCR_A, SBSC_SDCR_D1
  81
  82         write32 SBSC_SDWCR_A, SBSC_SDWCR_D
  83
  84         write32 SBSC_SDPCR_A, SBSC_SDPCR_D
  85
  86         write32 SBSC_RTCSR_A, SBSC_RTCSR_D
  87
  88         write32 SBSC_RTCNT_A, SBSC_RTCNT_D
  89
  90         write32 SBSC_RTCOR_A, SBSC_RTCOR_D
  91
  92         write8  SBSC_SDMR3_A1, SBSC_SDMR3_D
  93
  94         write8  SBSC_SDMR3_A2, SBSC_SDMR3_D
  95
  96         mov.l   SLEEP_CNT, r1
  97 2:      tst     r1, r1
  98         nop
  99         bf/s    2b
 100         dt      r1
 101
 102         write8  SBSC_SDMR3_A3, SBSC_SDMR3_D
 103
 104         write32 SBSC_SDCR_A, SBSC_SDCR_D2
 105
 106         write32 CCR_A, CCR_D
 107
 108         ! BL bit off (init = ON) (?!?)
 109
 110         stc     sr, r0                          ! BL bit off(init=ON)
 111         mov.l   SR_MASK_D, r1
 112         and     r1, r0
 113         ldc     r0, sr
 114
 115         rts
 116          mov    #0, r0
 117
 118         .align  2
 119
 120 DRVCRA_A:       .long   DRVCRA
 121 DRVCRB_A:       .long   DRVCRB
 122 DRVCRA_D:       .long   0x4555
 123 DRVCRB_D:       .long   0x0005
 124
 125 RWTCSR_A:       .long   RWTCSR
 126 RWTCNT_A:       .long   RWTCNT
 127 FRQCR_A:        .long   FRQCR
 128 RWTCSR_D1:      .long   0xa507
 129 RWTCSR_D2:      .long   0xa504
 130 RWTCNT_D:       .long   0x5a00
 131 FRQCR_D:        .long   0x0b04474a
 132
 133 SBSC_SDCR_A:    .long   SBSC_SDCR
 134 SBSC_SDWCR_A:   .long   SBSC_SDWCR
 135 SBSC_SDPCR_A:   .long   SBSC_SDPCR
 136 SBSC_RTCSR_A:   .long   SBSC_RTCSR
 137 SBSC_RTCNT_A:   .long   SBSC_RTCNT
 138 SBSC_RTCOR_A:   .long   SBSC_RTCOR
 139 SBSC_SDMR3_A1:  .long   0xfe510000
 140 SBSC_SDMR3_A2:  .long   0xfe500242
 141 SBSC_SDMR3_A3:  .long   0xfe5c0042
 142
 143 SBSC_SDCR_D1:   .long   0x92810112
 144 SBSC_SDCR_D2:   .long   0x92810912
 145 SBSC_SDWCR_D:   .long   0x05162482
 146 SBSC_SDPCR_D:   .long   0x00300087
 147 SBSC_RTCSR_D:   .long   0xa55a0212
 148 SBSC_RTCNT_D:   .long   0xa55a0000
 149 SBSC_RTCOR_D:   .long   0xa55a0040
 150 SBSC_SDMR3_D:   .long   0x00
 151
 152 CMNCR_A:        .long   CMNCR
 153 CS0BCR_A:       .long   CS0BCR
 154 CS4BCR_A:       .long   CS4BCR
 155 CS5ABCR_A:      .long   CS5ABCR
 156 CS5BBCR_A:      .long   CS5BBCR
 157 CS6ABCR_A:      .long   CS6ABCR
 158 CS6BBCR_A:      .long   CS6BBCR
 159 CS0WCR_A:       .long   CS0WCR
 160 CS4WCR_A:       .long   CS4WCR
 161 CS5AWCR_A:      .long   CS5AWCR
 162 CS5BWCR_A:      .long   CS5BWCR
 163 CS6AWCR_A:      .long   CS6AWCR
 164 CS6BWCR_A:      .long   CS6BWCR
 165
 166 CMNCR_D:        .long   0x00000013
 167 CS0BCR_D:       .long   0x24920400
 168 CS4BCR_D:       .long   0x24920400
 169 CS5ABCR_D:      .long   0x24920400
 170 CS5BBCR_D:      .long   0x7fff0600
 171 CS6ABCR_D:      .long   0x24920400
 172 CS6BBCR_D:      .long   0x24920600
 173 CS0WCR_D:       .long   0x00000480
 174 CS4WCR_D:       .long   0x00000480
 175 CS5AWCR_D:      .long   0x00000380
 176 CS5BWCR_D:      .long   0x00000600
 177 CS6AWCR_D:      .long   0x00000300
 178 CS6BWCR_D:      .long   0x00000540
 179
 180 CCR_A:          .long   0xff00001c
 181 CCR_D:          .long   0x0000090d
 182
 183 SLEEP_CNT:      .long   0x00000800
 184 SR_MASK_D:      .long   0xEFFFFF0F