board/renesas/gose/gose.c

   1 /*
   2  * board/renesas/gose/gose.c
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * SPDX-License-Identifier: GPL-2.0
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/processor.h>
  12 #include <asm/mach-types.h>
  13 #include <asm/io.h>
  14 #include <asm/errno.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/rmobile.h>
  18 #include <i2c.h>
  19 #include "qos.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  24 void s_init(void)
  25 {
  26         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  27         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  28         u32 stc;
  29
  30         /* Watchdog init */
  31         writel(0xA5A5A500, &rwdt->rwtcsra);
  32         writel(0xA5A5A500, &swdt->swtcsra);
  33
  34         /* CPU frequency setting. Set to 1.5GHz */
  35         stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  36         clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  37
  38         /* QoS */
  39         qos_init();
  40 }
  41
  42 #define MSTPSR1         0xE6150038
  43 #define SMSTPCR1        0xE6150134
  44 #define TMU0_MSTP125    (1 << 25)
  45
  46 #define MSTPSR7         0xE61501C4
  47 #define SMSTPCR7        0xE615014C
  48 #define SCIF0_MSTP721   (1 << 21)
  49
  50 #define mstp_setbits(type, addr, saddr, set) \
  51         out_##type((saddr), in_##type(addr) | (set))
  52 #define mstp_clrbits(type, addr, saddr, clear) \
  53         out_##type((saddr), in_##type(addr) & ~(clear))
  54 #define mstp_setbits_le32(addr, saddr, set) \
  55         mstp_setbits(le32, addr, saddr, set)
  56 #define mstp_clrbits_le32(addr, saddr, clear) \
  57         mstp_clrbits(le32, addr, saddr, clear)
  58
  59 int board_early_init_f(void)
  60 {
  61         /* TMU0 */
  62         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  63
  64         /* SCIF0 */
  65         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
  66
  67         return 0;
  68 }
  69
  70 #define TSTR0           0x04
  71 #define TSTR0_STR0      0x01
  72 void arch_preboot_os(void)
  73 {
  74         /* stop TMU0 */
  75         mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
  76         /* Disable TMU0 */
  77         mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  78 }
  79
  80 int board_init(void)
  81 {
  82         /* adress of boot parameters */
  83         gd->bd->bi_boot_params = GOSE_SDRAM_BASE + 0x100;
  84
  85         /* Init PFC controller */
  86         r8a7793_pinmux_init();
  87
  88         return 0;
  89 }
  90
  91 int dram_init(void)
  92 {
  93         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  94
  95         return 0;
  96 }
  97
  98 const struct rmobile_sysinfo sysinfo = {
  99         CONFIG_RMOBILE_BOARD_STRING
 100 };
 101
 102 void dram_init_banksize(void)
 103 {
 104         gd->bd->bi_dram[0].start = GOSE_SDRAM_BASE;
 105         gd->bd->bi_dram[0].size = GOSE_SDRAM_SIZE;
 106 }
 107
 108 void reset_cpu(ulong addr)
 109 {
 110         u8 val;
 111
 112         i2c_set_bus_num(2); /* PowerIC connected to ch2 */
 113         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 114         val |= 0x02;
 115         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 116 }