board/renesas/rcar-common/common.c

   1 /*
   2  * board/renesas/rcar-common/common.c
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   6  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/arch/rmobile.h>
  15 #include <asm/arch/rcar-mstp.h>
  16
  17 #define TSTR0           0x04
  18 #define TSTR0_STR0      0x01
  19
  20 static struct mstp_ctl mstptbl[] = {
  21         { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
  22                 RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
  23         { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
  24                 RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
  25         { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
  26                 RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
  27         { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
  28                 RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
  29         { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
  30                 RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
  31         { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
  32                 RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
  33 #ifdef CONFIG_RCAR_GEN3
  34         { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
  35                 RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
  36 #endif
  37         { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
  38                 RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
  39         { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
  40                 RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
  41         { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
  42                 RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
  43         { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
  44                  RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
  45         { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
  46                  RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
  47 };
  48
  49 void arch_preboot_os(void)
  50 {
  51         int i;
  52
  53         /* stop TMU0 */
  54         mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
  55
  56         /* Stop module clock */
  57         for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
  58                 mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
  59                                      mstptbl[i].s_ena);
  60                 mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
  61                                      mstptbl[i].r_ena);
  62         }
  63 }