board/renesas/sh7785lcr/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <config.h>
   7 #include <version.h>
   8 #include <asm/processor.h>
   9 #include <asm/macro.h>
  10
  11 #include <asm/processor.h>
  12
  13         .global lowlevel_init
  14
  15         .text
  16         .align  2
  17
  18 lowlevel_init:
  19         wait_timer      WAIT_200US
  20         wait_timer      WAIT_200US
  21
  22         /*------- LBSC -------*/
  23         write32 MMSELR_A,       MMSELR_D
  24
  25         /*------- DBSC2 -------*/
  26         write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
  27         write32 DBSC2_DBTR0_A,  DBSC2_DBTR0_D
  28         write32 DBSC2_DBTR1_A,  DBSC2_DBTR1_D
  29         write32 DBSC2_DBTR2_A,  DBSC2_DBTR2_D
  30         write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
  31         write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
  32         wait_timer      WAIT_200US
  33
  34         write32 DBSC2_DBDICODTOCD_A,    DBSC2_DBDICODTOCD_D
  35         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_CKE_H
  36         wait_timer      WAIT_200US
  37         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_PALL
  38         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS2
  39         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS3
  40         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_1
  41         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_MRS_1
  42         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_PALL
  43         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_REF
  44         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_REF
  45         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_MRS_2
  46         wait_timer      WAIT_200US
  47
  48         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_2
  49         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_1
  50
  51         write32 DBSC2_DBEN_A,           DBSC2_DBEN_D
  52         write32 DBSC2_DBRFCNT1_A,       DBSC2_DBRFCNT1_D
  53         write32 DBSC2_DBRFCNT2_A,       DBSC2_DBRFCNT2_D
  54         write32 DBSC2_DBRFCNT0_A,       DBSC2_DBRFCNT0_D
  55         wait_timer      WAIT_200US
  56
  57         /*------- GPIO -------*/
  58         write16 PACR_A, PXCR_D
  59         write16 PBCR_A, PXCR_D
  60         write16 PCCR_A, PXCR_D
  61         write16 PDCR_A, PXCR_D
  62         write16 PECR_A, PXCR_D
  63         write16 PFCR_A, PXCR_D
  64         write16 PGCR_A, PXCR_D
  65         write16 PHCR_A, PHCR_D
  66         write16 PJCR_A, PJCR_D
  67         write16 PKCR_A, PKCR_D
  68         write16 PLCR_A, PXCR_D
  69         write16 PMCR_A, PMCR_D
  70         write16 PNCR_A, PNCR_D
  71         write16 PPCR_A, PXCR_D
  72         write16 PQCR_A, PXCR_D
  73         write16 PRCR_A, PXCR_D
  74
  75         write8  PEPUPR_A,       PEPUPR_D
  76         write8  PHPUPR_A,       PHPUPR_D
  77         write8  PJPUPR_A,       PJPUPR_D
  78         write8  PKPUPR_A,       PKPUPR_D
  79         write8  PLPUPR_A,       PLPUPR_D
  80         write8  PMPUPR_A,       PMPUPR_D
  81         write8  PNPUPR_A,       PNPUPR_D
  82         write16 PPUPR1_A,       PPUPR1_D
  83         write16 PPUPR2_A,       PPUPR2_D
  84         write16 P1MSELR_A,      P1MSELR_D
  85         write16 P2MSELR_A,      P2MSELR_D
  86
  87         /*------- LBSC -------*/
  88         write32 BCR_A,          BCR_D
  89         write32 CS0BCR_A,       CS0BCR_D
  90         write32 CS0WCR_A,       CS0WCR_D
  91         write32 CS1BCR_A,       CS1BCR_D
  92         write32 CS1WCR_A,       CS1WCR_D
  93         write32 CS4BCR_A,       CS4BCR_D
  94         write32 CS4WCR_A,       CS4WCR_D
  95
  96         mov.l   PASCR_A, r0
  97         mov.l   @r0, r2
  98         mov.l   PASCR_32BIT_MODE, r1
  99         tst     r1, r2
 100         bt      lbsc_29bit
 101
 102         write32 CS2BCR_A,       CS_USB_BCR_D
 103         write32 CS2WCR_A,       CS_USB_WCR_D
 104         write32 CS3BCR_A,       CS_SD_BCR_D
 105         write32 CS3WCR_A,       CS_SD_WCR_D
 106         write32 CS5BCR_A,       CS_I2C_BCR_D
 107         write32 CS5WCR_A,       CS_I2C_WCR_D
 108         write32 CS6BCR_A,       CS0BCR_D
 109         write32 CS6WCR_A,       CS0WCR_D
 110         bra     lbsc_end
 111          nop
 112
 113 lbsc_29bit:
 114         write32 CS5BCR_A,       CS_USB_BCR_D
 115         write32 CS5WCR_A,       CS_USB_WCR_D
 116         write32 CS6BCR_A,       CS_SD_BCR_D
 117         write32 CS6WCR_A,       CS_SD_WCR_D
 118
 119 lbsc_end:
 120 #if defined(CONFIG_SH_32BIT)
 121         /*------- set PMB -------*/
 122         write32 PASCR_A,        PASCR_29BIT_D
 123         write32 MMUCR_A,        MMUCR_D
 124
 125         /*****************************************************************
 126          * ent  virt            phys            v       sz      c       wt
 127          * 0    0xa0000000      0x00000000      1       64M     0       0
 128          * 1    0xa4000000      0x04000000      1       16M     0       0
 129          * 2    0xa6000000      0x08000000      1       16M     0       0
 130          * 9    0x88000000      0x48000000      1       128M    1       1
 131          * 10   0x90000000      0x50000000      1       128M    1       1
 132          * 11   0x98000000      0x58000000      1       128M    1       1
 133          * 13   0xa8000000      0x48000000      1       128M    0       0
 134          * 14   0xb0000000      0x50000000      1       128M    0       0
 135          * 15   0xb8000000      0x58000000      1       128M    0       0
 136          */
 137         write32 PMB_ADDR_FLASH_A,       PMB_ADDR_FLASH_D
 138         write32 PMB_DATA_FLASH_A,       PMB_DATA_FLASH_D
 139         write32 PMB_ADDR_CPLD_A,        PMB_ADDR_CPLD_D
 140         write32 PMB_DATA_CPLD_A,        PMB_DATA_CPLD_D
 141         write32 PMB_ADDR_USB_A,         PMB_ADDR_USB_D
 142         write32 PMB_DATA_USB_A,         PMB_DATA_USB_D
 143         write32 PMB_ADDR_DDR_C1_A,      PMB_ADDR_DDR_C1_D
 144         write32 PMB_DATA_DDR_C1_A,      PMB_DATA_DDR_C1_D
 145         write32 PMB_ADDR_DDR_C2_A,      PMB_ADDR_DDR_C2_D
 146         write32 PMB_DATA_DDR_C2_A,      PMB_DATA_DDR_C2_D
 147         write32 PMB_ADDR_DDR_C3_A,      PMB_ADDR_DDR_C3_D
 148         write32 PMB_DATA_DDR_C3_A,      PMB_DATA_DDR_C3_D
 149         write32 PMB_ADDR_DDR_N1_A,      PMB_ADDR_DDR_N1_D
 150         write32 PMB_DATA_DDR_N1_A,      PMB_DATA_DDR_N1_D
 151         write32 PMB_ADDR_DDR_N2_A,      PMB_ADDR_DDR_N2_D
 152         write32 PMB_DATA_DDR_N2_A,      PMB_DATA_DDR_N2_D
 153         write32 PMB_ADDR_DDR_N3_A,      PMB_ADDR_DDR_N3_D
 154         write32 PMB_DATA_DDR_N3_A,      PMB_DATA_DDR_N3_D
 155
 156         write32 PASCR_A,        PASCR_INIT
 157         mov.l   DUMMY_ADDR, r0
 158         icbi    @r0
 159 #endif
 160
 161         write32 CCR_A,  CCR_D
 162
 163         rts
 164         nop
 165
 166         .align 4
 167
 168 /*------- GPIO -------*/
 169 /* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
 170 PXCR_D:         .word   0x0000
 171
 172 PHCR_D:         .word   0x00c0
 173 PJCR_D:         .word   0xc3fc
 174 PKCR_D:         .word   0x03ff
 175 PMCR_D:         .word   0xffff
 176 PNCR_D:         .word   0xf0c3
 177
 178 PEPUPR_D:       .long   0xff
 179 PHPUPR_D:       .long   0x00
 180 PJPUPR_D:       .long   0x00
 181 PKPUPR_D:       .long   0x00
 182 PLPUPR_D:       .long   0x00
 183 PMPUPR_D:       .long   0xfc
 184 PNPUPR_D:       .long   0x00
 185 PPUPR1_D:       .word   0xffbf
 186 PPUPR2_D:       .word   0xff00
 187 P1MSELR_D:      .word   0x3780
 188 P2MSELR_D:      .word   0x0000
 189
 190 #define GPIO_BASE       0xffe70000
 191 PACR_A:         .long   GPIO_BASE + 0x00
 192 PBCR_A:         .long   GPIO_BASE + 0x02
 193 PCCR_A:         .long   GPIO_BASE + 0x04
 194 PDCR_A:         .long   GPIO_BASE + 0x06
 195 PECR_A:         .long   GPIO_BASE + 0x08
 196 PFCR_A:         .long   GPIO_BASE + 0x0a
 197 PGCR_A:         .long   GPIO_BASE + 0x0c
 198 PHCR_A:         .long   GPIO_BASE + 0x0e
 199 PJCR_A:         .long   GPIO_BASE + 0x10
 200 PKCR_A:         .long   GPIO_BASE + 0x12
 201 PLCR_A:         .long   GPIO_BASE + 0x14
 202 PMCR_A:         .long   GPIO_BASE + 0x16
 203 PNCR_A:         .long   GPIO_BASE + 0x18
 204 PPCR_A:         .long   GPIO_BASE + 0x1a
 205 PQCR_A:         .long   GPIO_BASE + 0x1c
 206 PRCR_A:         .long   GPIO_BASE + 0x1e
 207 PEPUPR_A:       .long   GPIO_BASE + 0x48
 208 PHPUPR_A:       .long   GPIO_BASE + 0x4e
 209 PJPUPR_A:       .long   GPIO_BASE + 0x50
 210 PKPUPR_A:       .long   GPIO_BASE + 0x52
 211 PLPUPR_A:       .long   GPIO_BASE + 0x54
 212 PMPUPR_A:       .long   GPIO_BASE + 0x56
 213 PNPUPR_A:       .long   GPIO_BASE + 0x58
 214 PPUPR1_A:       .long   GPIO_BASE + 0x60
 215 PPUPR2_A:       .long   GPIO_BASE + 0x62
 216 P1MSELR_A:      .long   GPIO_BASE + 0x80
 217 P2MSELR_A:      .long   GPIO_BASE + 0x82
 218
 219 MMSELR_A:      .long   0xfc400020
 220 #if defined(CONFIG_SH_32BIT)
 221 MMSELR_D:      .long   0xa5a50005
 222 #else
 223 MMSELR_D:      .long   0xa5a50002
 224 #endif
 225
 226 /*------- DBSC2 -------*/
 227 #define DBSC2_BASE      0xfe800000
 228 DBSC2_DBSTATE_A:        .long   DBSC2_BASE + 0x0c
 229 DBSC2_DBEN_A:           .long   DBSC2_BASE + 0x10
 230 DBSC2_DBCMDCNT_A:       .long   DBSC2_BASE + 0x14
 231 DBSC2_DBCONF_A:         .long   DBSC2_BASE + 0x20
 232 DBSC2_DBTR0_A:          .long   DBSC2_BASE + 0x30
 233 DBSC2_DBTR1_A:          .long   DBSC2_BASE + 0x34
 234 DBSC2_DBTR2_A:          .long   DBSC2_BASE + 0x38
 235 DBSC2_DBRFCNT0_A:       .long   DBSC2_BASE + 0x40
 236 DBSC2_DBRFCNT1_A:       .long   DBSC2_BASE + 0x44
 237 DBSC2_DBRFCNT2_A:       .long   DBSC2_BASE + 0x48
 238 DBSC2_DBRFSTS_A:        .long   DBSC2_BASE + 0x4c
 239 DBSC2_DBFREQ_A:         .long   DBSC2_BASE + 0x50
 240 DBSC2_DBDICODTOCD_A:.long       DBSC2_BASE + 0x54
 241 DBSC2_DBMRCNT_A:        .long   DBSC2_BASE + 0x60
 242 DDR_DUMMY_ACCESS_A:     .long   0x40000000
 243
 244 DBSC2_DBCONF_D:         .long   0x00630002
 245 DBSC2_DBTR0_D:          .long   0x050b1f04
 246 DBSC2_DBTR1_D:          .long   0x00040204
 247 DBSC2_DBTR2_D:          .long   0x02100308
 248 DBSC2_DBFREQ_D1:        .long   0x00000000
 249 DBSC2_DBFREQ_D2:        .long   0x00000100
 250 DBSC2_DBDICODTOCD_D:.long       0x000f0907
 251
 252 DBSC2_DBCMDCNT_D_CKE_H: .long   0x00000003
 253 DBSC2_DBCMDCNT_D_PALL:  .long   0x00000002
 254 DBSC2_DBCMDCNT_D_REF:   .long   0x00000004
 255
 256 DBSC2_DBMRCNT_D_EMRS2:  .long   0x00020000
 257 DBSC2_DBMRCNT_D_EMRS3:  .long   0x00030000
 258 DBSC2_DBMRCNT_D_EMRS1_1:        .long   0x00010006
 259 DBSC2_DBMRCNT_D_EMRS1_2:        .long   0x00010386
 260 DBSC2_DBMRCNT_D_MRS_1:  .long   0x00000952
 261 DBSC2_DBMRCNT_D_MRS_2:  .long   0x00000852
 262
 263 DBSC2_DBEN_D:           .long   0x00000001
 264
 265 DBSC2_DBPDCNT0_D3:      .long   0x00000080
 266 DBSC2_DBRFCNT1_D:       .long   0x00000926
 267 DBSC2_DBRFCNT2_D:       .long   0x00fe00fe
 268 DBSC2_DBRFCNT0_D:       .long   0x00010000
 269
 270 WAIT_200US:    .long   33333
 271
 272 /*------- LBSC -------*/
 273 PASCR_A:                .long   0xff000070
 274 PASCR_32BIT_MODE:       .long   0x80000000      /* check booting mode */
 275
 276 BCR_A:          .long   BCR
 277 CS0BCR_A:       .long   CS0BCR
 278 CS0WCR_A:       .long   CS0WCR
 279 CS1BCR_A:       .long   CS1BCR
 280 CS1WCR_A:       .long   CS1WCR
 281 CS2BCR_A:       .long   CS2BCR
 282 CS2WCR_A:       .long   CS2WCR
 283 CS3BCR_A:       .long   CS3BCR
 284 CS3WCR_A:       .long   CS3WCR
 285 CS4BCR_A:       .long   CS4BCR
 286 CS4WCR_A:       .long   CS4WCR
 287 CS5BCR_A:       .long   CS5BCR
 288 CS5WCR_A:       .long   CS5WCR
 289 CS6BCR_A:       .long   CS6BCR
 290 CS6WCR_A:       .long   CS6WCR
 291
 292 BCR_D:          .long   0x80000003
 293 CS0BCR_D:       .long   0x22222340
 294 CS0WCR_D:       .long   0x00111118
 295 CS1BCR_D:       .long   0x11111100
 296 CS1WCR_D:       .long   0x33333303
 297 CS4BCR_D:       .long   0x11111300
 298 CS4WCR_D:       .long   0x00101012
 299
 300 /* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
 301 CS_USB_BCR_D:   .long   0x11111200
 302 CS_USB_WCR_D:   .long   0x00020005
 303
 304 /* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
 305 CS_SD_BCR_D:    .long   0x00000300
 306 CS_SD_WCR_D:    .long   0x00030108
 307
 308 /* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
 309 CS_I2C_BCR_D:   .long   0x11111100
 310 CS_I2C_WCR_D:   .long   0x00000003
 311
 312 #if defined(CONFIG_SH_32BIT)
 313 /*------- set PMB -------*/
 314 PMB_ADDR_FLASH_A:       .long   PMB_ADDR_BASE(0)
 315 PMB_ADDR_CPLD_A:        .long   PMB_ADDR_BASE(1)
 316 PMB_ADDR_USB_A:         .long   PMB_ADDR_BASE(2)
 317 PMB_ADDR_DDR_C1_A:      .long   PMB_ADDR_BASE(9)
 318 PMB_ADDR_DDR_C2_A:      .long   PMB_ADDR_BASE(10)
 319 PMB_ADDR_DDR_C3_A:      .long   PMB_ADDR_BASE(11)
 320 PMB_ADDR_DDR_N1_A:      .long   PMB_ADDR_BASE(13)
 321 PMB_ADDR_DDR_N2_A:      .long   PMB_ADDR_BASE(14)
 322 PMB_ADDR_DDR_N3_A:      .long   PMB_ADDR_BASE(15)
 323
 324 PMB_ADDR_FLASH_D:       .long   mk_pmb_addr_val(0xa0)
 325 PMB_ADDR_CPLD_D:        .long   mk_pmb_addr_val(0xa4)
 326 PMB_ADDR_USB_D:         .long   mk_pmb_addr_val(0xa6)
 327 PMB_ADDR_DDR_C1_D:      .long   mk_pmb_addr_val(0x88)
 328 PMB_ADDR_DDR_C2_D:      .long   mk_pmb_addr_val(0x90)
 329 PMB_ADDR_DDR_C3_D:      .long   mk_pmb_addr_val(0x98)
 330 PMB_ADDR_DDR_N1_D:      .long   mk_pmb_addr_val(0xa8)
 331 PMB_ADDR_DDR_N2_D:      .long   mk_pmb_addr_val(0xb0)
 332 PMB_ADDR_DDR_N3_D:      .long   mk_pmb_addr_val(0xb8)
 333
 334 PMB_DATA_FLASH_A:       .long   PMB_DATA_BASE(0)
 335 PMB_DATA_CPLD_A:        .long   PMB_DATA_BASE(1)
 336 PMB_DATA_USB_A:         .long   PMB_DATA_BASE(2)
 337 PMB_DATA_DDR_C1_A:      .long   PMB_DATA_BASE(9)
 338 PMB_DATA_DDR_C2_A:      .long   PMB_DATA_BASE(10)
 339 PMB_DATA_DDR_C3_A:      .long   PMB_DATA_BASE(11)
 340 PMB_DATA_DDR_N1_A:      .long   PMB_DATA_BASE(13)
 341 PMB_DATA_DDR_N2_A:      .long   PMB_DATA_BASE(14)
 342 PMB_DATA_DDR_N3_A:      .long   PMB_DATA_BASE(15)
 343
 344 /*                                              ppn   ub v s1 s0  c  wt */
 345 PMB_DATA_FLASH_D:       .long   mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
 346 PMB_DATA_CPLD_D:        .long   mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
 347 PMB_DATA_USB_D:         .long   mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
 348 PMB_DATA_DDR_C1_D:      .long   mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
 349 PMB_DATA_DDR_C2_D:      .long   mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
 350 PMB_DATA_DDR_C3_D:      .long   mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
 351 PMB_DATA_DDR_N1_D:      .long   mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
 352 PMB_DATA_DDR_N2_D:      .long   mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
 353 PMB_DATA_DDR_N3_D:      .long   mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
 354
 355 DUMMY_ADDR:     .long   0xa0000000
 356 PASCR_29BIT_D:  .long   0x00000000
 357 PASCR_INIT:     .long   0x80000080      /* check booting mode */
 358 MMUCR_A:        .long   0xff000010
 359 MMUCR_D:        .long   0x00000004      /* clear ITLB */
 360 #endif  /* CONFIG_SH_32BIT */
 361
 362 CCR_A:          .long   0xff00001c
 363 CCR_D:          .long   0x0000090b