board/renesas/silk/silk.c

   1 /*
   2  * board/renesas/silk/silk.c
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Cogent Embedded, Inc.
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <dm.h>
  13 #include <dm/platform_data/serial_sh.h>
  14 #include <asm/processor.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/io.h>
  17 #include <asm/errno.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/gpio.h>
  20 #include <asm/arch/rmobile.h>
  21 #include <asm/arch/rcar-mstp.h>
  22 #include <asm/arch/mmc.h>
  23 #include <netdev.h>
  24 #include <miiphy.h>
  25 #include <i2c.h>
  26 #include <div64.h>
  27 #include "qos.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  32 void s_init(void)
  33 {
  34         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  35         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  36
  37         /* Watchdog init */
  38         writel(0xA5A5A500, &rwdt->rwtcsra);
  39         writel(0xA5A5A500, &swdt->swtcsra);
  40
  41         /* QoS */
  42         qos_init();
  43 }
  44
  45 #define TMU0_MSTP125    (1 << 25)
  46 #define SCIF2_MSTP719   (1 << 19)
  47 #define ETHER_MSTP813   (1 << 13)
  48 #define IIC1_MSTP323    (1 << 23)
  49 #define MMC0_MSTP315    (1 << 15)
  50
  51 int board_early_init_f(void)
  52 {
  53         /* TMU */
  54         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  55
  56         /* SCIF2 */
  57         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  58
  59         /* ETHER */
  60         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  61
  62         /* IIC1 / sh-i2c ch1 */
  63         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
  64
  65 #ifdef CONFIG_SH_MMCIF
  66         /* MMC */
  67         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
  68 #endif
  69         return 0;
  70 }
  71
  72 int board_init(void)
  73 {
  74         /* adress of boot parameters */
  75         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  76
  77         /* Init PFC controller */
  78         r8a7794_pinmux_init();
  79
  80         /* Ether Enable */
  81         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  82         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  83         gpio_request(GPIO_FN_ETH_RXD0, NULL);
  84         gpio_request(GPIO_FN_ETH_RXD1, NULL);
  85         gpio_request(GPIO_FN_ETH_LINK, NULL);
  86         gpio_request(GPIO_FN_ETH_REFCLK, NULL);
  87         gpio_request(GPIO_FN_ETH_MDIO, NULL);
  88         gpio_request(GPIO_FN_ETH_TXD1, NULL);
  89         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
  90         gpio_request(GPIO_FN_ETH_MAGIC, NULL);
  91         gpio_request(GPIO_FN_ETH_TXD0, NULL);
  92         gpio_request(GPIO_FN_ETH_MDC, NULL);
  93         gpio_request(GPIO_FN_IRQ8, NULL);
  94
  95         /* PHY reset */
  96         gpio_request(GPIO_GP_1_24, NULL);
  97         gpio_direction_output(GPIO_GP_1_24, 0);
  98         mdelay(20);
  99         gpio_set_value(GPIO_GP_1_24, 1);
 100         udelay(1);
 101
 102         return 0;
 103 }
 104
 105 #define CXR24 0xEE7003C0 /* MAC address high register */
 106 #define CXR25 0xEE7003C8 /* MAC address low register */
 107 int board_eth_init(bd_t *bis)
 108 {
 109 #ifdef CONFIG_SH_ETHER
 110         int ret = -ENODEV;
 111         u32 val;
 112         unsigned char enetaddr[6];
 113
 114         ret = sh_eth_initialize(bis);
 115         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 116                 return ret;
 117
 118         /* Set Mac address */
 119         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 120                 enetaddr[2] << 8 | enetaddr[3];
 121         writel(val, CXR24);
 122
 123         val = enetaddr[4] << 8 | enetaddr[5];
 124         writel(val, CXR25);
 125
 126         return ret;
 127 #else
 128         return 0;
 129 #endif
 130 }
 131
 132 int board_mmc_init(bd_t *bis)
 133 {
 134         int ret = 0;
 135
 136 #ifdef CONFIG_SH_MMCIF
 137         /* MMC0 */
 138         gpio_request(GPIO_GP_4_31, NULL);
 139         gpio_set_value(GPIO_GP_4_31, 1);
 140
 141         ret = mmcif_mmc_init();
 142 #endif
 143         return ret;
 144 }
 145
 146 int dram_init(void)
 147 {
 148         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 149
 150         return 0;
 151 }
 152
 153 const struct rmobile_sysinfo sysinfo = {
 154         CONFIG_RMOBILE_BOARD_STRING
 155 };
 156
 157 void reset_cpu(ulong addr)
 158 {
 159         u8 val;
 160
 161         i2c_set_bus_num(1); /* PowerIC connected to ch1 */
 162         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 163         val |= 0x02;
 164         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 165 }
 166
 167 static const struct sh_serial_platdata serial_platdata = {
 168         .base = SCIF2_BASE,
 169         .type = PORT_SCIF,
 170         .clk = 14745600,
 171         .clk_mode = EXT_CLK,
 172 };
 173
 174 U_BOOT_DEVICE(alt_serials) = {
 175         .name = "serial_sh",
 176         .platdata = &serial_platdata,
 177 };