2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/sizes.h>
29 #include <asm/arch/at91sam9263.h>
30 #include <asm/arch/at91sam9263_matrix.h>
31 #include <asm/arch/at91sam9_smc.h>
32 #include <asm/arch/at91_common.h>
33 #include <asm/arch/at91_pmc.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/clk.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/io.h>
38 #include <asm/arch/hardware.h>
40 #include <atmel_lcdc.h>
41 #include <dataflash.h>
42 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
47 DECLARE_GLOBAL_DATA_PTR
;
49 /* ------------------------------------------------------------------------- */
51 * Miscelaneous platform dependent initialisations
54 #ifdef CONFIG_CMD_NAND
55 static void pm9263_nand_hw_init(void)
60 csa
= at91_sys_read(AT91_MATRIX_EBI0CSA
);
61 at91_sys_write(AT91_MATRIX_EBI0CSA
,
62 csa
| AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA
);
64 /* Configure SMC CS3 for NAND/SmartMedia */
65 at91_sys_write(AT91_SMC_SETUP(3),
66 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
67 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
68 at91_sys_write(AT91_SMC_PULSE(3),
69 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
70 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
71 at91_sys_write(AT91_SMC_CYCLE(3),
72 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
73 at91_sys_write(AT91_SMC_MODE(3),
74 AT91_SMC_READMODE
| AT91_SMC_WRITEMODE
|
75 AT91_SMC_EXNWMODE_DISABLE
|
76 #ifdef CONFIG_SYS_NAND_DBW_16
78 #else /* CONFIG_SYS_NAND_DBW_8 */
83 /* Configure RDY/BSY */
84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
86 /* Enable NandFlash */
87 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
92 static void pm9263_macb_hw_init(void)
95 * PB27 enables the 50MHz oscillator for Ethernet PHY
99 at91_set_gpio_output(AT91_PIN_PB27
, 1);
100 at91_set_gpio_value(AT91_PIN_PB27
, 1); /* 1- enable, 0 - disable */
103 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9263_ID_EMAC
);
106 * Disable pull-up on:
107 * RXDV (PC25) => PHY normal mode (not Test mode)
108 * ERX0 (PE25) => PHY ADDR0
109 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
111 * PHY has internal pull-down
113 writel(pin_to_mask(AT91_PIN_PC25
),
114 pin_to_controller(AT91_PIN_PC0
) + PIO_PUDR
);
115 writel(pin_to_mask(AT91_PIN_PE25
) |
116 pin_to_mask(AT91_PIN_PE26
),
117 pin_to_controller(AT91_PIN_PE0
) + PIO_PUDR
);
120 /* Re-enable pull-up */
121 writel(pin_to_mask(AT91_PIN_PC25
),
122 pin_to_controller(AT91_PIN_PC0
) + PIO_PUER
);
123 writel(pin_to_mask(AT91_PIN_PE25
) |
124 pin_to_mask(AT91_PIN_PE26
),
125 pin_to_controller(AT91_PIN_PE0
) + PIO_PUER
);
132 vidinfo_t panel_info
= {
136 vl_sync
: ATMEL_LCDC_INVLINE_INVERTED
|
137 ATMEL_LCDC_INVFRAME_INVERTED
,
146 mmio
: AT91SAM9263_LCDC_BASE
,
149 void lcd_enable(void)
151 at91_set_gpio_value(AT91_PIN_PA22
, 1); /* power up */
154 void lcd_disable(void)
156 at91_set_gpio_value(AT91_PIN_PA22
, 0); /* power down */
159 #ifdef CONFIG_LCD_IN_PSRAM
161 #define PSRAM_CRE_PIN AT91_PIN_PB29
162 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
164 /* Initialize the PSRAM memory */
165 static int pm9263_lcd_hw_psram_init(void)
169 /* setup PB29 as output */
170 at91_set_gpio_output(PSRAM_CRE_PIN
, 1);
172 at91_set_gpio_value(PSRAM_CRE_PIN
, 0); /* set PSRAM_CRE_PIN to '0' */
174 /* PSRAM: write BCR */
175 x
= readw(PSRAM_CTRL_REG
);
176 x
= readw(PSRAM_CTRL_REG
);
177 writew(1, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
178 writew(0x9d4f, PSRAM_CTRL_REG
); /* write the BCR */
180 /* write RCR of the PSRAM */
181 x
= readw(PSRAM_CTRL_REG
);
182 x
= readw(PSRAM_CTRL_REG
);
183 writew(0, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
184 /* set RCR; 0x10-async mode,0x90-page mode */
185 writew(0x90, PSRAM_CTRL_REG
);
188 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
189 * MT45W2M16B - CRE must be 0
190 * MT45W2M16A - CRE must be 1
192 writew(0x1234, PHYS_PSRAM
);
193 writew(0x5678, PHYS_PSRAM
+ 2);
195 /* test if the chip is MT45W2M16B */
196 if ((readw(PHYS_PSRAM
) != 0x1234) || (readw(PHYS_PSRAM
+2) != 0x5678)) {
197 /* try with CRE=1 (MT45W2M16A) */
198 at91_set_gpio_value(PSRAM_CRE_PIN
, 1); /* set PSRAM_CRE_PIN to '1' */
200 /* write RCR of the PSRAM */
201 x
= readw(PSRAM_CTRL_REG
);
202 x
= readw(PSRAM_CTRL_REG
);
203 writew(0, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
204 /* set RCR;0x10-async mode,0x90-page mode */
205 writew(0x90, PSRAM_CTRL_REG
);
208 writew(0x1234, PHYS_PSRAM
);
209 writew(0x5678, PHYS_PSRAM
+2);
210 if ((readw(PHYS_PSRAM
) != 0x1234)
211 || (readw(PHYS_PSRAM
+ 2) != 0x5678))
217 at91_sys_write( AT91_MATRIX_PRAS5
, AT91_MATRIX_M5PR
);
218 at91_sys_write( AT91_MATRIX_SCFG5
, AT91_MATRIX_ARBT_FIXED_PRIORITY
|
219 (AT91_MATRIX_FIXED_DEFMSTR
& (5 << 18)) |
220 AT91_MATRIX_DEFMSTR_TYPE_FIXED
|
221 (AT91_MATRIX_SLOT_CYCLE
& (0x80 << 0)));
227 static void pm9263_lcd_hw_init(void)
229 at91_set_A_periph(AT91_PIN_PC0
, 0); /* LCDVSYNC */
230 at91_set_A_periph(AT91_PIN_PC1
, 0); /* LCDHSYNC */
231 at91_set_A_periph(AT91_PIN_PC2
, 0); /* LCDDOTCK */
232 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDDEN */
233 at91_set_B_periph(AT91_PIN_PB9
, 0); /* LCDCC */
234 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDD2 */
235 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDD3 */
236 at91_set_A_periph(AT91_PIN_PC8
, 0); /* LCDD4 */
237 at91_set_A_periph(AT91_PIN_PC9
, 0); /* LCDD5 */
238 at91_set_A_periph(AT91_PIN_PC10
, 0); /* LCDD6 */
239 at91_set_A_periph(AT91_PIN_PC11
, 0); /* LCDD7 */
240 at91_set_A_periph(AT91_PIN_PC14
, 0); /* LCDD10 */
241 at91_set_A_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
242 at91_set_A_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
243 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD13 */
244 at91_set_A_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
245 at91_set_A_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
246 at91_set_A_periph(AT91_PIN_PC22
, 0); /* LCDD18 */
247 at91_set_A_periph(AT91_PIN_PC23
, 0); /* LCDD19 */
248 at91_set_A_periph(AT91_PIN_PC24
, 0); /* LCDD20 */
249 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD21 */
250 at91_set_A_periph(AT91_PIN_PC26
, 0); /* LCDD22 */
251 at91_set_A_periph(AT91_PIN_PC27
, 0); /* LCDD23 */
253 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9263_ID_LCDC
);
256 at91_set_gpio_output(AT91_PIN_PA22
, 1);
257 at91_set_gpio_value(AT91_PIN_PA22
, 0); /* power down */
259 #ifdef CONFIG_LCD_IN_PSRAM
260 /* initialize te PSRAM */
261 int stat
= pm9263_lcd_hw_psram_init();
263 gd
->fb_base
= (stat
== 0) ? PHYS_PSRAM
: AT91SAM9263_SRAM0_BASE
;
265 gd
->fb_base
= AT91SAM9263_SRAM0_BASE
;
270 #ifdef CONFIG_LCD_INFO
274 extern flash_info_t flash_info
[];
276 void lcd_show_board_info(void)
278 ulong dram_size
, nand_size
, flash_size
, dataflash_size
;
282 lcd_printf ("%s\n", U_BOOT_VERSION
);
283 lcd_printf ("(C) 2009 Ronetix GmbH\n");
284 lcd_printf ("support@ronetix.at\n");
285 lcd_printf ("%s CPU at %s MHz",
287 strmhz(temp
, get_cpu_clk_rate()));
290 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
291 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
294 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
295 nand_size
+= nand_info
[i
].size
;
298 for (i
= 0; i
< CONFIG_SYS_MAX_FLASH_BANKS
; i
++)
299 flash_size
+= flash_info
[i
].size
;
302 for (i
= 0; i
< CONFIG_SYS_MAX_DATAFLASH_BANKS
; i
++)
303 dataflash_size
+= (unsigned int) dataflash_info
[i
].Device
.pages_number
*
304 dataflash_info
[i
].Device
.pages_size
;
306 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
307 "4 MB PSRAM, %ld MB DataFlash\n",
311 dataflash_size
>> 20);
313 #endif /* CONFIG_LCD_INFO */
315 #endif /* CONFIG_LCD */
322 at91_sys_write(AT91_PMC_PCER
,
323 (1 << AT91SAM9263_ID_PIOA
) |
324 (1 << AT91SAM9263_ID_PIOCDE
) |
325 (1 << AT91SAM9263_ID_PIOB
));
327 /* arch number of AT91SAM9263EK-Board */
328 gd
->bd
->bi_arch_number
= MACH_TYPE_PM9263
;
330 /* adress of boot parameters */
331 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
333 at91_serial_hw_init();
334 #ifdef CONFIG_CMD_NAND
335 pm9263_nand_hw_init();
337 #ifdef CONFIG_HAS_DATAFLASH
338 at91_spi0_hw_init(1 << 0);
341 pm9263_macb_hw_init();
343 #ifdef CONFIG_USB_OHCI_NEW
347 pm9263_lcd_hw_init();
354 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM
;
355 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_SIZE
;
359 #ifdef CONFIG_RESET_PHY_R
364 * Initialize ethernet HW addr prior to starting Linux,
372 int board_eth_init(bd_t
*bis
)
376 rc
= macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC
, 0x01);
381 #ifdef CONFIG_DISPLAY_BOARDINFO
382 int checkboard (void)
387 printf ("Board : Ronetix PM9263\n");
388 printf ("Crystal frequency: %8s MHz\n",
389 strmhz(buf
, get_main_clk_rate()));
390 printf ("CPU clock : %8s MHz\n",
391 strmhz(buf
, get_cpu_clk_rate()));
392 printf ("Master clock : %8s MHz\n",
393 strmhz(buf
, get_mck_clk_rate()));
395 switch (gd
->fb_base
) {
400 case AT91SAM9263_SRAM0_BASE
:
401 ss
= "(Internal SRAM)";
408 printf("Video memory : 0x%08lX %s\n", gd
->fb_base
, ss
);