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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013 SAMSUNG Electronics
4 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
5 */
6
7 #include <common.h>
8 #include <cros_ec.h>
9 #include <errno.h>
10 #include <fdtdec.h>
11 #include <hang.h>
12 #include <init.h>
13 #include <spi.h>
14 #include <tmu.h>
15 #include <netdev.h>
16 #include <asm/io.h>
17 #include <asm/gpio.h>
18 #include <asm/arch/board.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/dwmmc.h>
21 #include <asm/arch/mmc.h>
22 #include <asm/arch/pinmux.h>
23 #include <asm/arch/power.h>
24 #include <asm/arch/system.h>
25 #include <asm/arch/sromc.h>
26 #include <lcd.h>
27 #include <i2c.h>
28 #include <mmc.h>
29 #include <stdio_dev.h>
30 #include <usb.h>
31 #include <dwc3-uboot.h>
32 #include <samsung/misc.h>
33 #include <dm/pinctrl.h>
34 #include <dm.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 __weak int exynos_early_init_f(void)
39 {
40 return 0;
41 }
42
43 __weak int exynos_power_init(void)
44 {
45 return 0;
46 }
47
48 /**
49 * get_boot_mmc_dev() - read boot MMC device id from XOM[7:5] pins.
50 */
51 static int get_boot_mmc_dev(void)
52 {
53 u32 mode = readl(EXYNOS4_OP_MODE) & 0x1C;
54
55 if (mode == 0x04)
56 return 2; /* MMC2: SD */
57
58 /* MMC0: eMMC or unknown */
59 return 0;
60 }
61
62 #if defined CONFIG_EXYNOS_TMU
63 /* Boot Time Thermal Analysis for SoC temperature threshold breach */
64 static void boot_temp_check(void)
65 {
66 int temp;
67
68 switch (tmu_monitor(&temp)) {
69 case TMU_STATUS_NORMAL:
70 break;
71 case TMU_STATUS_TRIPPED:
72 /*
73 * Status TRIPPED ans WARNING means corresponding threshold
74 * breach
75 */
76 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
77 set_ps_hold_ctrl();
78 hang();
79 break;
80 case TMU_STATUS_WARNING:
81 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
82 break;
83 case TMU_STATUS_INIT:
84 /*
85 * TMU_STATUS_INIT means something is wrong with temperature
86 * sensing and TMU status was changed back from NORMAL to INIT.
87 */
88 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
89 break;
90 default:
91 debug("EXYNOS_TMU: Unknown TMU state\n");
92 }
93 }
94 #endif
95
96 int board_init(void)
97 {
98 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
99 #if defined CONFIG_EXYNOS_TMU
100 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
101 debug("%s: Failed to init TMU\n", __func__);
102 return -1;
103 }
104 boot_temp_check();
105 #endif
106 #ifdef CONFIG_TZSW_RESERVED_DRAM_SIZE
107 /* The last few MB of memory can be reserved for secure firmware */
108 ulong size = CONFIG_TZSW_RESERVED_DRAM_SIZE;
109
110 gd->ram_size -= size;
111 gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size;
112 #endif
113 return exynos_init();
114 }
115
116 int dram_init(void)
117 {
118 unsigned int i;
119 unsigned long addr;
120
121 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
122 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
123 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
124 }
125 return 0;
126 }
127
128 int dram_init_banksize(void)
129 {
130 unsigned int i;
131 unsigned long addr, size;
132
133 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
134 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
135 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
136
137 gd->bd->bi_dram[i].start = addr;
138 gd->bd->bi_dram[i].size = size;
139 }
140
141 return 0;
142 }
143
144 static int board_uart_init(void)
145 {
146 #ifndef CONFIG_PINCTRL_EXYNOS
147 int err, uart_id, ret = 0;
148
149 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
150 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
151 if (err) {
152 debug("UART%d not configured\n",
153 (uart_id - PERIPH_ID_UART0));
154 ret |= err;
155 }
156 }
157 return ret;
158 #else
159 return 0;
160 #endif
161 }
162
163 #ifdef CONFIG_BOARD_EARLY_INIT_F
164 int board_early_init_f(void)
165 {
166 int err;
167 #ifdef CONFIG_BOARD_TYPES
168 set_board_type();
169 #endif
170 err = board_uart_init();
171 if (err) {
172 debug("UART init failed\n");
173 return err;
174 }
175
176 #ifdef CONFIG_SYS_I2C_INIT_BOARD
177 board_i2c_init(gd->fdt_blob);
178 #endif
179
180 return exynos_early_init_f();
181 }
182 #endif
183
184 #if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC)
185 int power_init_board(void)
186 {
187 set_ps_hold_ctrl();
188
189 return exynos_power_init();
190 }
191 #endif
192
193 #ifdef CONFIG_SMC911X
194 static int decode_sromc(const void *blob, struct fdt_sromc *config)
195 {
196 int err;
197 int node;
198
199 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
200 if (node < 0) {
201 debug("Could not find SROMC node\n");
202 return node;
203 }
204
205 config->bank = fdtdec_get_int(blob, node, "bank", 0);
206 config->width = fdtdec_get_int(blob, node, "width", 2);
207
208 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
209 FDT_SROM_TIMING_COUNT);
210 if (err < 0) {
211 debug("Could not decode SROMC configuration Error: %s\n",
212 fdt_strerror(err));
213 return -FDT_ERR_NOTFOUND;
214 }
215 return 0;
216 }
217 #endif
218
219 int board_eth_init(bd_t *bis)
220 {
221 #ifdef CONFIG_SMC911X
222 u32 smc_bw_conf, smc_bc_conf;
223 struct fdt_sromc config;
224 fdt_addr_t base_addr;
225 int node;
226
227 node = decode_sromc(gd->fdt_blob, &config);
228 if (node < 0) {
229 debug("%s: Could not find sromc configuration\n", __func__);
230 return 0;
231 }
232 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
233 if (node < 0) {
234 debug("%s: Could not find lan9215 configuration\n", __func__);
235 return 0;
236 }
237
238 /* We now have a node, so any problems from now on are errors */
239 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
240 if (base_addr == FDT_ADDR_T_NONE) {
241 debug("%s: Could not find lan9215 address\n", __func__);
242 return -1;
243 }
244
245 /* Ethernet needs data bus width of 16 bits */
246 if (config.width != 2) {
247 debug("%s: Unsupported bus width %d\n", __func__,
248 config.width);
249 return -1;
250 }
251 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
252 | SROMC_BYTE_ENABLE(config.bank);
253
254 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
255 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
256 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
257 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
258 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
259 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
260 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
261
262 /* Select and configure the SROMC bank */
263 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
264 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
265 return smc911x_initialize(0, base_addr);
266 #endif
267 return 0;
268 }
269
270 #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
271 int checkboard(void)
272 {
273 if (IS_ENABLED(CONFIG_BOARD_TYPES)) {
274 const char *board_info;
275
276 if (IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
277 /*
278 * Printing type requires having revision, although
279 * this will succeed only if done late.
280 * Otherwise revision will be set in misc_init_r().
281 */
282 set_board_revision();
283 }
284
285 board_info = get_board_type();
286
287 if (board_info)
288 printf("Type: %s\n", board_info);
289 }
290
291 return 0;
292 }
293 #endif
294
295 #ifdef CONFIG_BOARD_LATE_INIT
296 int board_late_init(void)
297 {
298 struct udevice *dev;
299 int ret;
300 int mmcbootdev = get_boot_mmc_dev();
301 char mmcbootdev_str[16];
302
303 stdio_print_current_devices();
304 ret = uclass_first_device_err(UCLASS_CROS_EC, &dev);
305 if (ret && ret != -ENODEV) {
306 /* Force console on */
307 gd->flags &= ~GD_FLG_SILENT;
308
309 printf("cros-ec communications failure %d\n", ret);
310 puts("\nPlease reset with Power+Refresh\n\n");
311 panic("Cannot init cros-ec device");
312 return -1;
313 }
314
315 printf("Boot device: MMC(%u)\n", mmcbootdev);
316 sprintf(mmcbootdev_str, "%u", mmcbootdev);
317 env_set("mmcbootdev", mmcbootdev_str);
318
319 return 0;
320 }
321 #endif
322
323 #ifdef CONFIG_MISC_INIT_R
324 int misc_init_r(void)
325 {
326 if (IS_ENABLED(CONFIG_BOARD_TYPES) &&
327 !IS_ENABLED(CONFIG_DISPLAY_BOARDINFO_LATE)) {
328 /*
329 * If revision was not set by late display boardinfo,
330 * set it here. At this point regulators should be already
331 * available.
332 */
333 set_board_revision();
334 }
335
336 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
337 set_board_info();
338 #endif
339 #ifdef CONFIG_LCD_MENU
340 keys_init();
341 check_boot_mode();
342 #endif
343 #ifdef CONFIG_CMD_BMP
344 if (panel_info.logo_on)
345 draw_logo();
346 #endif
347 return 0;
348 }
349 #endif
350
351 void reset_misc(void)
352 {
353 struct gpio_desc gpio = {};
354 int node;
355
356 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
357 "samsung,emmc-reset");
358 if (node < 0)
359 return;
360
361 gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0,
362 &gpio, GPIOD_IS_OUT);
363
364 if (dm_gpio_is_valid(&gpio)) {
365 /*
366 * Reset eMMC
367 *
368 * FIXME: Need to optimize delay time. Minimum 1usec pulse is
369 * required by 'JEDEC Standard No.84-A441' (eMMC)
370 * document but real delay time is expected to greater
371 * than 1usec.
372 */
373 dm_gpio_set_value(&gpio, 0);
374 mdelay(10);
375 dm_gpio_set_value(&gpio, 1);
376 }
377 }
378
379 int board_usb_cleanup(int index, enum usb_init_type init)
380 {
381 #ifdef CONFIG_USB_DWC3
382 dwc3_uboot_exit(index);
383 #endif
384 return 0;
385 }
386
387 int mmc_get_env_dev(void)
388 {
389 return get_boot_mmc_dev();
390 }