2 * Copyright (C) 2014 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/power.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
14 #include <asm/arch/cpu.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
18 #include <power/max77686_pmic.h>
22 #include <usb/dwc2_udc.h>
23 #include <samsung/misc.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 #ifdef CONFIG_BOARD_TYPES
29 /* Odroid board types */
36 void set_board_type(void)
38 /* Set GPA1 pin 1 to HI - enable XCL205 output */
39 writel(XCL205_EN_GPIO_CON_CFG
, XCL205_EN_GPIO_CON
);
40 writel(XCL205_EN_GPIO_DAT_CFG
, XCL205_EN_GPIO_CON
+ 0x4);
41 writel(XCL205_EN_GPIO_PUD_CFG
, XCL205_EN_GPIO_CON
+ 0x8);
42 writel(XCL205_EN_GPIO_DRV_CFG
, XCL205_EN_GPIO_CON
+ 0xc);
44 /* Set GPC1 pin 2 to IN - check XCL205 output state */
45 writel(XCL205_STATE_GPIO_CON_CFG
, XCL205_STATE_GPIO_CON
);
46 writel(XCL205_STATE_GPIO_PUD_CFG
, XCL205_STATE_GPIO_CON
+ 0x8);
48 /* XCL205 - needs some latch time */
51 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
52 if (readl(XCL205_STATE_GPIO_DAT
) & (1 << XCL205_STATE_GPIO_PIN
))
53 gd
->board_type
= ODROID_TYPE_X2
;
55 gd
->board_type
= ODROID_TYPE_U3
;
58 const char *get_board_type(void)
60 const char *board_type
[] = {"u3", "x2"};
62 return board_type
[gd
->board_type
];
66 #ifdef CONFIG_SET_DFU_ALT_INFO
67 char *get_dfu_alt_system(char *interface
, char *devstr
)
69 return env_get("dfu_alt_system");
72 char *get_dfu_alt_boot(char *interface
, char *devstr
)
78 dev_num
= simple_strtoul(devstr
, NULL
, 10);
80 mmc
= find_mmc_device(dev_num
);
87 alt_boot
= IS_SD(mmc
) ? CONFIG_DFU_ALT_BOOT_SD
:
88 CONFIG_DFU_ALT_BOOT_EMMC
;
94 static void board_clock_init(void)
96 unsigned int set
, clr
, clr_src_cpu
, clr_pll_con0
, clr_src_dmc
;
97 struct exynos4x12_clock
*clk
= (struct exynos4x12_clock
*)
98 samsung_get_base_clock();
101 * CMU_CPU clocks src to MPLL
103 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
104 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
105 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
106 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
108 clr_src_cpu
= MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
109 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
110 set
= MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
111 MUX_MPLL_USER_SEL_C(1);
113 clrsetbits_le32(&clk
->src_cpu
, clr_src_cpu
, set
);
115 /* Wait for mux change */
116 while (readl(&clk
->mux_stat_cpu
) & MUX_STAT_CPU_CHANGING
)
119 /* Set APLL to 1000MHz */
120 clr_pll_con0
= SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
121 set
= SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
123 clrsetbits_le32(&clk
->apll_con0
, clr_pll_con0
, set
);
125 /* Wait for PLL to be locked */
126 while (!(readl(&clk
->apll_con0
) & PLL_LOCKED_BIT
))
129 /* Set CMU_CPU clocks src to APLL */
130 set
= MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
131 MUX_MPLL_USER_SEL_C(1);
132 clrsetbits_le32(&clk
->src_cpu
, clr_src_cpu
, set
);
134 /* Wait for mux change */
135 while (readl(&clk
->mux_stat_cpu
) & MUX_STAT_CPU_CHANGING
)
138 set
= CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
139 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
140 APLL_RATIO(0) | CORE2_RATIO(0);
142 * Set dividers for MOUTcore = 1000 MHz
143 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
144 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
145 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
146 * periph = armclk / (ratio + 1) = 1000 MHz (0)
147 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
148 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
149 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
150 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
152 clr
= CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
153 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
154 APLL_RATIO(7) | CORE2_RATIO(7);
156 clrsetbits_le32(&clk
->div_cpu0
, clr
, set
);
158 /* Wait for divider ready status */
159 while (readl(&clk
->div_stat_cpu0
) & DIV_STAT_CPU0_CHANGING
)
163 * For MOUThpm = 1000 MHz (MOUTapll)
164 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
165 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
166 * cores_out = armclk / (ratio + 1) = 200 (4)
168 clr
= COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
169 set
= COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
171 clrsetbits_le32(&clk
->div_cpu1
, clr
, set
);
173 /* Wait for divider ready status */
174 while (readl(&clk
->div_stat_cpu1
) & DIV_STAT_CPU1_CHANGING
)
178 * Set CMU_DMC clocks src to APLL
180 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
181 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
182 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
183 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
184 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
185 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
186 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
187 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
189 clr_src_dmc
= MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
190 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
191 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
192 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
193 set
= MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
194 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
195 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
197 clrsetbits_le32(&clk
->src_dmc
, clr_src_dmc
, set
);
199 /* Wait for mux change */
200 while (readl(&clk
->mux_stat_dmc
) & MUX_STAT_DMC_CHANGING
)
203 /* Set MPLL to 800MHz */
204 set
= SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
206 clrsetbits_le32(&clk
->mpll_con0
, clr_pll_con0
, set
);
208 /* Wait for PLL to be locked */
209 while (!(readl(&clk
->mpll_con0
) & PLL_LOCKED_BIT
))
212 /* Switch back CMU_DMC mux */
213 set
= MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
214 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
215 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
217 clrsetbits_le32(&clk
->src_dmc
, clr_src_dmc
, set
);
219 /* Wait for mux change */
220 while (readl(&clk
->mux_stat_dmc
) & MUX_STAT_DMC_CHANGING
)
224 clr
= ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
225 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
231 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
232 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
233 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
234 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
235 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
236 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
238 set
= ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
239 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
241 clrsetbits_le32(&clk
->div_dmc0
, clr
, set
);
243 /* Wait for divider ready status */
244 while (readl(&clk
->div_stat_dmc0
) & DIV_STAT_DMC0_CHANGING
)
248 clr
= G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
249 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
256 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
257 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
258 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
259 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
261 set
= G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
262 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
264 clrsetbits_le32(&clk
->div_dmc1
, clr
, set
);
266 /* Wait for divider ready status */
267 while (readl(&clk
->div_stat_dmc1
) & DIV_STAT_DMC1_CHANGING
)
271 clr
= UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
272 UART3_SEL(15) | UART4_SEL(15);
274 * Set CLK_SRC_PERIL0 clocks src to MPLL
275 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
276 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
279 * Set all to SCLK_MPLL_USER_T
281 set
= UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
284 clrsetbits_le32(&clk
->src_peril0
, clr
, set
);
287 clr
= UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
288 UART3_RATIO(15) | UART4_RATIO(15);
290 * For MOUTuart0-4: 800MHz
292 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
294 set
= UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
295 UART3_RATIO(7) | UART4_RATIO(7);
297 clrsetbits_le32(&clk
->div_peril0
, clr
, set
);
299 while (readl(&clk
->div_stat_peril0
) & DIV_STAT_PERIL0_CHANGING
)
303 clr
= MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
306 * For MOUTmmc0-3 = 800 MHz (MPLL)
308 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
309 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
310 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
311 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
313 set
= MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
316 clrsetbits_le32(&clk
->div_fsys1
, clr
, set
);
318 /* Wait for divider ready status */
319 while (readl(&clk
->div_stat_fsys1
) & DIV_STAT_FSYS1_CHANGING
)
323 clr
= MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
326 * For MOUTmmc0-3 = 800 MHz (MPLL)
328 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
329 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
330 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
331 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
333 set
= MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
336 clrsetbits_le32(&clk
->div_fsys2
, clr
, set
);
338 /* Wait for divider ready status */
339 while (readl(&clk
->div_stat_fsys2
) & DIV_STAT_FSYS2_CHANGING
)
343 clr
= MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
345 * For MOUTmmc4 = 800 MHz (MPLL)
347 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
348 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
350 set
= MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
352 clrsetbits_le32(&clk
->div_fsys3
, clr
, set
);
354 /* Wait for divider ready status */
355 while (readl(&clk
->div_stat_fsys3
) & DIV_STAT_FSYS3_CHANGING
)
361 static void board_gpio_init(void)
364 gpio_request(EXYNOS4X12_GPIO_K12
, "eMMC Reset");
366 gpio_cfg_pin(EXYNOS4X12_GPIO_K12
, S5P_GPIO_FUNC(0x1));
367 gpio_set_pull(EXYNOS4X12_GPIO_K12
, S5P_GPIO_PULL_NONE
);
368 gpio_set_drv(EXYNOS4X12_GPIO_K12
, S5P_GPIO_DRV_4X
);
370 /* Enable FAN (Odroid U3) */
371 gpio_request(EXYNOS4X12_GPIO_D00
, "FAN Control");
373 gpio_set_pull(EXYNOS4X12_GPIO_D00
, S5P_GPIO_PULL_UP
);
374 gpio_set_drv(EXYNOS4X12_GPIO_D00
, S5P_GPIO_DRV_4X
);
375 gpio_direction_output(EXYNOS4X12_GPIO_D00
, 1);
377 /* OTG Vbus output (Odroid U3+) */
378 gpio_request(EXYNOS4X12_GPIO_L20
, "OTG Vbus");
380 gpio_set_pull(EXYNOS4X12_GPIO_L20
, S5P_GPIO_PULL_NONE
);
381 gpio_set_drv(EXYNOS4X12_GPIO_L20
, S5P_GPIO_DRV_4X
);
382 gpio_direction_output(EXYNOS4X12_GPIO_L20
, 0);
384 /* OTG INT (Odroid U3+) */
385 gpio_request(EXYNOS4X12_GPIO_X31
, "OTG INT");
387 gpio_set_pull(EXYNOS4X12_GPIO_X31
, S5P_GPIO_PULL_UP
);
388 gpio_set_drv(EXYNOS4X12_GPIO_X31
, S5P_GPIO_DRV_4X
);
389 gpio_direction_input(EXYNOS4X12_GPIO_X31
);
391 /* Blue LED (Odroid X2/U2/U3) */
392 gpio_request(EXYNOS4X12_GPIO_C10
, "Blue LED");
394 gpio_direction_output(EXYNOS4X12_GPIO_C10
, 0);
396 #ifdef CONFIG_CMD_USB
397 /* USB3503A Reference frequency */
398 gpio_request(EXYNOS4X12_GPIO_X30
, "USB3503A RefFreq");
400 /* USB3503A Connect */
401 gpio_request(EXYNOS4X12_GPIO_X34
, "USB3503A Connect");
404 gpio_request(EXYNOS4X12_GPIO_X35
, "USB3503A Reset");
408 int exynos_early_init_f(void)
415 int exynos_init(void)
422 int exynos_power_init(void)
424 const char *mmc_regulators
[] = {
431 if (regulator_list_autoset(mmc_regulators
, NULL
, true))
432 error("Unable to init all mmc regulators");
437 #ifdef CONFIG_USB_GADGET
438 static int s5pc210_phy_control(int on
)
443 ret
= regulator_get_by_platname("VDD_UOTG_3.0V", &dev
);
445 error("Regulator get error: %d", ret
);
450 return regulator_set_mode(dev
, OPMODE_ON
);
452 return regulator_set_mode(dev
, OPMODE_LPM
);
455 struct dwc2_plat_otg_data s5pc210_otg_data
= {
456 .phy_control
= s5pc210_phy_control
,
457 .regs_phy
= EXYNOS4X12_USBPHY_BASE
,
458 .regs_otg
= EXYNOS4X12_USBOTG_BASE
,
459 .usb_phy_ctrl
= EXYNOS4X12_USBPHY_CONTROL
,
460 .usb_flags
= PHY0_SLEEP
,
464 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
466 int board_usb_init(int index
, enum usb_init_type init
)
468 #ifdef CONFIG_CMD_USB
472 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
473 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
474 if (gd
->board_type
== ODROID_TYPE_U3
)
475 gpio_direction_output(EXYNOS4X12_GPIO_X30
, 0);
477 gpio_direction_output(EXYNOS4X12_GPIO_X30
, 1);
479 /* Disconnect, Reset, Connect */
480 gpio_direction_output(EXYNOS4X12_GPIO_X34
, 0);
481 gpio_direction_output(EXYNOS4X12_GPIO_X35
, 0);
482 gpio_direction_output(EXYNOS4X12_GPIO_X35
, 1);
483 gpio_direction_output(EXYNOS4X12_GPIO_X34
, 1);
485 /* Power off and on BUCK8 for LAN9730 */
486 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
488 ret
= regulator_get_by_platname("VCC_P3V3_2.85V", &dev
);
490 error("Regulator get error: %d", ret
);
494 ret
= regulator_set_enable(dev
, true);
496 error("Regulator %s enable setting error: %d", dev
->name
, ret
);
500 ret
= regulator_set_value(dev
, 750000);
502 error("Regulator %s value setting error: %d", dev
->name
, ret
);
506 ret
= regulator_set_value(dev
, 3300000);
508 error("Regulator %s value setting error: %d", dev
->name
, ret
);
512 debug("USB_udc_probe\n");
513 return dwc2_udc_probe(&s5pc210_otg_data
);