board/samsung/origen/lowlevel_init.S

   1 /*
   2  * Lowlevel setup for ORIGEN board based on EXYNOS4210
   3  *
   4  * Copyright (C) 2011 Samsung Electronics
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <version.h>
  27 #include <asm/arch/cpu.h>
  28 #include "origen_setup.h"
  29 /*
  30  * Register usages:
  31  *
  32  * r5 has zero always
  33  * r7 has GPIO part1 base 0x11400000
  34  * r6 has GPIO part2 base 0x11000000
  35  */
  36
  37 _TEXT_BASE:
  38         .word   CONFIG_SYS_TEXT_BASE
  39
  40         .globl lowlevel_init
  41 lowlevel_init:
  42         push    {lr}
  43
  44         /* r5 has always zero */
  45         mov     r5, #0
  46         ldr     r7, =EXYNOS4_GPIO_PART1_BASE
  47         ldr     r6, =EXYNOS4_GPIO_PART2_BASE
  48
  49         /* check reset status */
  50         ldr     r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
  51         ldr     r1, [r0]
  52
  53         /* AFTR wakeup reset */
  54         ldr     r2, =S5P_CHECK_DIDLE
  55         cmp     r1, r2
  56         beq     exit_wakeup
  57
  58         /* LPA wakeup reset */
  59         ldr     r2, =S5P_CHECK_LPA
  60         cmp     r1, r2
  61         beq     exit_wakeup
  62
  63         /* Sleep wakeup reset */
  64         ldr     r2, =S5P_CHECK_SLEEP
  65         cmp     r1, r2
  66         beq     wakeup_reset
  67
  68         /*
  69          * If U-boot is already running in ram, no need to relocate U-Boot.
  70          * Memory controller must be configured before relocating U-Boot
  71          * in ram.
  72          */
  73         ldr     r0, =0x0ffffff          /* r0 <- Mask Bits*/
  74         bic     r1, pc, r0              /* pc <- current addr of code */
  75                                         /* r1 <- unmasked bits of pc */
  76         ldr     r2, _TEXT_BASE          /* r2 <- original base addr in ram */
  77         bic     r2, r2, r0              /* r2 <- unmasked bits of r2*/
  78         cmp     r1, r2                  /* compare r1, r2 */
  79         beq     1f                      /* r0 == r1 then skip sdram init */
  80
  81         /* init system clock */
  82         bl system_clock_init
  83
  84         /* Memory initialize */
  85         bl mem_ctrl_asm_init
  86
  87 1:
  88         /* for UART */
  89         bl uart_asm_init
  90         bl arch_cpu_init
  91         bl tzpc_init
  92         pop     {pc}
  93
  94 wakeup_reset:
  95         bl system_clock_init
  96         bl mem_ctrl_asm_init
  97         bl arch_cpu_init
  98         bl tzpc_init
  99
 100 exit_wakeup:
 101         /* Load return address and jump to kernel */
 102         ldr     r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
 103
 104         /* r1 = physical address of exynos4210_cpu_resume function */
 105         ldr     r1, [r0]
 106
 107         /* Jump to kernel*/
 108         mov     pc, r1
 109         nop
 110         nop
 111
 112 /*
 113  * system_clock_init: Initialize core clock and bus clock.
 114  * void system_clock_init(void)
 115  */
 116 system_clock_init:
 117         push    {lr}
 118         ldr     r0, =EXYNOS4_CLOCK_BASE
 119
 120         /* APLL(1), MPLL(1), CORE(0), HPM(0) */
 121         ldr     r1, =CLK_SRC_CPU_VAL
 122         ldr     r2, =CLK_SRC_CPU_OFFSET
 123         str     r1, [r0, r2]
 124
 125         /* wait ?us */
 126         mov     r1, #0x10000
 127 2:      subs    r1, r1, #1
 128         bne     2b
 129
 130         ldr     r1, =CLK_SRC_TOP0_VAL
 131         ldr     r2, =CLK_SRC_TOP0_OFFSET
 132         str     r1, [r0, r2]
 133
 134         ldr     r1, =CLK_SRC_TOP1_VAL
 135         ldr     r2, =CLK_SRC_TOP1_OFFSET
 136         str     r1, [r0, r2]
 137
 138         /* DMC */
 139         ldr     r1, =CLK_SRC_DMC_VAL
 140         ldr     r2, =CLK_SRC_DMC_OFFSET
 141         str     r1, [r0, r2]
 142
 143         /*CLK_SRC_LEFTBUS */
 144         ldr     r1, =CLK_SRC_LEFTBUS_VAL
 145         ldr     r2, =CLK_SRC_LEFTBUS_OFFSET
 146         str     r1, [r0, r2]
 147
 148         /*CLK_SRC_RIGHTBUS */
 149         ldr     r1, =CLK_SRC_RIGHTBUS_VAL
 150         ldr     r2, =CLK_SRC_RIGHTBUS_OFFSET
 151         str     r1, [r0, r2]
 152
 153         /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
 154         ldr     r1, =CLK_SRC_FSYS_VAL
 155         ldr     r2, =CLK_SRC_FSYS_OFFSET
 156         str     r1, [r0, r2]
 157
 158         /* UART[0:4] */
 159         ldr     r1, =CLK_SRC_PERIL0_VAL
 160         ldr     r2, =CLK_SRC_PERIL0_OFFSET
 161         str     r1, [r0, r2]
 162
 163         /* CAM , FIMC 0-3 */
 164         ldr     r1, =CLK_SRC_CAM_VAL
 165         ldr     r2, =CLK_SRC_CAM_OFFSET
 166         str     r1, [r0, r2]
 167
 168         /* MFC */
 169         ldr     r1, =CLK_SRC_MFC_VAL
 170         ldr     r2, =CLK_SRC_MFC_OFFSET
 171         str     r1, [r0, r2]
 172
 173         /* G3D */
 174         ldr     r1, =CLK_SRC_G3D_VAL
 175         ldr     r2, =CLK_SRC_G3D_OFFSET
 176         str     r1, [r0, r2]
 177
 178         /* LCD0 */
 179         ldr     r1, =CLK_SRC_LCD0_VAL
 180         ldr     r2, =CLK_SRC_LCD0_OFFSET
 181         str     r1, [r0, r2]
 182
 183         /* wait ?us */
 184         mov     r1, #0x10000
 185 3:      subs    r1, r1, #1
 186         bne     3b
 187
 188         /* CLK_DIV_CPU0 */
 189         ldr     r1, =CLK_DIV_CPU0_VAL
 190         ldr     r2, =CLK_DIV_CPU0_OFFSET
 191         str     r1, [r0, r2]
 192
 193         /* CLK_DIV_CPU1 */
 194         ldr     r1, =CLK_DIV_CPU1_VAL
 195         ldr     r2, =CLK_DIV_CPU1_OFFSET
 196         str     r1, [r0, r2]
 197
 198         /* CLK_DIV_DMC0 */
 199         ldr     r1, =CLK_DIV_DMC0_VAL
 200         ldr     r2, =CLK_DIV_DMC0_OFFSET
 201         str     r1, [r0, r2]
 202
 203         /*CLK_DIV_DMC1 */
 204         ldr     r1, =CLK_DIV_DMC1_VAL
 205         ldr     r2, =CLK_DIV_DMC1_OFFSET
 206         str     r1, [r0, r2]
 207
 208         /* CLK_DIV_LEFTBUS */
 209         ldr     r1, =CLK_DIV_LEFTBUS_VAL
 210         ldr     r2, =CLK_DIV_LEFTBUS_OFFSET
 211         str     r1, [r0, r2]
 212
 213         /* CLK_DIV_RIGHTBUS */
 214         ldr     r1, =CLK_DIV_RIGHTBUS_VAL
 215         ldr     r2, =CLK_DIV_RIGHTBUS_OFFSET
 216         str     r1, [r0, r2]
 217
 218         /* CLK_DIV_TOP */
 219         ldr     r1, =CLK_DIV_TOP_VAL
 220         ldr     r2, =CLK_DIV_TOP_OFFSET
 221         str     r1, [r0, r2]
 222
 223         /* MMC[0:1] */
 224         ldr     r1, =CLK_DIV_FSYS1_VAL          /* 800(MPLL) / (15 + 1) */
 225         ldr     r2, =CLK_DIV_FSYS1_OFFSET
 226         str     r1, [r0, r2]
 227
 228         /* MMC[2:3] */
 229         ldr     r1, =CLK_DIV_FSYS2_VAL          /* 800(MPLL) / (15 + 1) */
 230         ldr     r2, =CLK_DIV_FSYS2_OFFSET
 231         str     r1, [r0, r2]
 232
 233         /* MMC4 */
 234         ldr     r1, =CLK_DIV_FSYS3_VAL          /* 800(MPLL) / (15 + 1) */
 235         ldr     r2, =CLK_DIV_FSYS3_OFFSET
 236         str     r1, [r0, r2]
 237
 238         /* CLK_DIV_PERIL0: UART Clock Divisors */
 239         ldr     r1, =CLK_DIV_PERIL0_VAL
 240         ldr     r2, =CLK_DIV_PERIL0_OFFSET
 241         str     r1, [r0, r2]
 242
 243         /* CAM, FIMC 0-3: CAM Clock Divisors */
 244         ldr     r1, =CLK_DIV_CAM_VAL
 245         ldr     r2, =CLK_DIV_CAM_OFFSET
 246         str     r1, [r0, r2]
 247
 248         /* CLK_DIV_MFC: MFC Clock Divisors */
 249         ldr     r1, =CLK_DIV_MFC_VAL
 250         ldr     r2, =CLK_DIV_MFC_OFFSET
 251         str     r1, [r0, r2]
 252
 253         /* CLK_DIV_G3D: G3D Clock Divisors */
 254         ldr     r1, =CLK_DIV_G3D_VAL
 255         ldr     r2, =CLK_DIV_G3D_OFFSET
 256         str     r1, [r0, r2]
 257
 258         /* CLK_DIV_LCD0: LCD0 Clock Divisors */
 259         ldr     r1, =CLK_DIV_LCD0_VAL
 260         ldr     r2, =CLK_DIV_LCD0_OFFSET
 261         str     r1, [r0, r2]
 262
 263         /* Set PLL locktime */
 264         ldr     r1, =PLL_LOCKTIME
 265         ldr     r2, =APLL_LOCK_OFFSET
 266         str     r1, [r0, r2]
 267
 268         ldr     r1, =PLL_LOCKTIME
 269         ldr     r2, =MPLL_LOCK_OFFSET
 270         str     r1, [r0, r2]
 271
 272         ldr     r1, =PLL_LOCKTIME
 273         ldr     r2, =EPLL_LOCK_OFFSET
 274         str     r1, [r0, r2]
 275
 276         ldr     r1, =PLL_LOCKTIME
 277         ldr     r2, =VPLL_LOCK_OFFSET
 278         str     r1, [r0, r2]
 279
 280         /* APLL_CON1 */
 281         ldr     r1, =APLL_CON1_VAL
 282         ldr     r2, =APLL_CON1_OFFSET
 283         str     r1, [r0, r2]
 284
 285         /* APLL_CON0 */
 286         ldr     r1, =APLL_CON0_VAL
 287         ldr     r2, =APLL_CON0_OFFSET
 288         str     r1, [r0, r2]
 289
 290         /* MPLL_CON1 */
 291         ldr     r1, =MPLL_CON1_VAL
 292         ldr     r2, =MPLL_CON1_OFFSET
 293         str     r1, [r0, r2]
 294
 295         /* MPLL_CON0 */
 296         ldr     r1, =MPLL_CON0_VAL
 297         ldr     r2, =MPLL_CON0_OFFSET
 298         str     r1, [r0, r2]
 299
 300         /* EPLL */
 301         ldr     r1, =EPLL_CON1_VAL
 302         ldr     r2, =EPLL_CON1_OFFSET
 303         str     r1, [r0, r2]
 304
 305         /* EPLL_CON0 */
 306         ldr     r1, =EPLL_CON0_VAL
 307         ldr     r2, =EPLL_CON0_OFFSET
 308         str     r1, [r0, r2]
 309
 310         /* VPLL_CON1 */
 311         ldr     r1, =VPLL_CON1_VAL
 312         ldr     r2, =VPLL_CON1_OFFSET
 313         str     r1, [r0, r2]
 314
 315         /* VPLL_CON0 */
 316         ldr     r1, =VPLL_CON0_VAL
 317         ldr     r2, =VPLL_CON0_OFFSET
 318         str     r1, [r0, r2]
 319
 320         /* wait ?us */
 321         mov     r1, #0x30000
 322 4:      subs    r1, r1, #1
 323         bne     4b
 324
 325         pop     {pc}
 326 /*
 327  * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
 328  * void uart_asm_init(void)
 329  */
 330         .globl uart_asm_init
 331 uart_asm_init:
 332
 333         /* setup UART0-UART3 GPIOs (part1) */
 334         mov     r0, r7
 335         ldr     r1, =EXYNOS4_GPIO_A0_CON_VAL
 336         str     r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
 337         ldr     r1, =EXYNOS4_GPIO_A1_CON_VAL
 338         str     r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
 339
 340         ldr r0, =EXYNOS4_UART_BASE
 341         add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
 342
 343         ldr     r1, =ULCON_VAL
 344         str     r1, [r0, #ULCON_OFFSET]
 345         ldr     r1, =UCON_VAL
 346         str     r1, [r0, #UCON_OFFSET]
 347         ldr     r1, =UFCON_VAL
 348         str     r1, [r0, #UFCON_OFFSET]
 349         ldr     r1, =UBRDIV_VAL
 350         str     r1, [r0, #UBRDIV_OFFSET]
 351         ldr     r1, =UFRACVAL_VAL
 352         str     r1, [r0, #UFRACVAL_OFFSET]
 353         mov     pc, lr
 354         nop
 355         nop
 356         nop
 357