]>
git.ipfire.org Git - thirdparty/u-boot.git/blob - board/samsung/smdk2410/smdk2410.c
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * (C) Copyright 2002, 2010
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/s3c24x0_cpu.h>
17 DECLARE_GLOBAL_DATA_PTR
;
21 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
25 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
43 static inline void pll_delay(unsigned long loops
)
45 __asm__
volatile ("1:\n"
47 "bne 1b":"=r" (loops
):"0" (loops
));
51 * Miscellaneous platform dependent initialisations
54 int board_early_init_f(void)
56 struct s3c24x0_clock_power
* const clk_power
=
57 s3c24x0_get_base_clock_power();
58 struct s3c24x0_gpio
* const gpio
= s3c24x0_get_base_gpio();
60 /* to reduce PLL lock time, adjust the LOCKTIME register */
61 writel(0xFFFFFF, &clk_power
->locktime
);
64 writel((M_MDIV
<< 12) + (M_PDIV
<< 4) + M_SDIV
,
67 /* some delay between MPLL and UPLL */
71 writel((U_M_MDIV
<< 12) + (U_M_PDIV
<< 4) + U_M_SDIV
,
74 /* some delay between MPLL and UPLL */
77 /* set up the I/O ports */
78 writel(0x007FFFFF, &gpio
->gpacon
);
79 writel(0x00044555, &gpio
->gpbcon
);
80 writel(0x000007FF, &gpio
->gpbup
);
81 writel(0xAAAAAAAA, &gpio
->gpccon
);
82 writel(0x0000FFFF, &gpio
->gpcup
);
83 writel(0xAAAAAAAA, &gpio
->gpdcon
);
84 writel(0x0000FFFF, &gpio
->gpdup
);
85 writel(0xAAAAAAAA, &gpio
->gpecon
);
86 writel(0x0000FFFF, &gpio
->gpeup
);
87 writel(0x000055AA, &gpio
->gpfcon
);
88 writel(0x000000FF, &gpio
->gpfup
);
89 writel(0xFF95FFBA, &gpio
->gpgcon
);
90 writel(0x0000FFFF, &gpio
->gpgup
);
91 writel(0x002AFAAA, &gpio
->gphcon
);
92 writel(0x000007FF, &gpio
->gphup
);
99 /* arch number of SMDK2410-Board */
100 gd
->bd
->bi_arch_number
= MACH_TYPE_SMDK2410
;
102 /* adress of boot parameters */
103 gd
->bd
->bi_boot_params
= 0x30000100;
113 /* dram_init must store complete ramsize in gd->ram_size */
114 gd
->ram_size
= PHYS_SDRAM_1_SIZE
;
118 #ifdef CONFIG_CMD_NET
119 int board_eth_init(bd_t
*bis
)
123 rc
= cs8900_initialize(0, CONFIG_CS8900_BASE
);
130 * Hardcoded flash setup:
131 * Flash 0 is a non-CFI AMD AM29LV800BB flash.
133 ulong
board_flash_get_legacy(ulong base
, int banknum
, flash_info_t
*info
)
135 info
->portwidth
= FLASH_CFI_16BIT
;
136 info
->chipwidth
= FLASH_CFI_BY16
;
137 info
->interface
= FLASH_CFI_X16
;