board/samsung/smdk5250/exynos5-dt.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <cros_ec.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <errno.h>
  12 #include <i2c.h>
  13 #include <netdev.h>
  14 #include <spi.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/dwmmc.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc.h>
  19 #include <asm/arch/pinmux.h>
  20 #include <asm/arch/power.h>
  21 #include <asm/arch/sromc.h>
  22 #include <power/pmic.h>
  23 #include <power/max77686_pmic.h>
  24 #include <tmu.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #if defined CONFIG_EXYNOS_TMU
  29 /*
  30  * Boot Time Thermal Analysis for SoC temperature threshold breach
  31  */
  32 static void boot_temp_check(void)
  33 {
  34         int temp;
  35
  36         switch (tmu_monitor(&temp)) {
  37         /* Status TRIPPED ans WARNING means corresponding threshold breach */
  38         case TMU_STATUS_TRIPPED:
  39                 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
  40                 set_ps_hold_ctrl();
  41                 hang();
  42                 break;
  43         case TMU_STATUS_WARNING:
  44                 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
  45                 break;
  46         /*
  47          * TMU_STATUS_INIT means something is wrong with temperature sensing
  48          * and TMU status was changed back from NORMAL to INIT.
  49          */
  50         case TMU_STATUS_INIT:
  51         default:
  52                 debug("EXYNOS_TMU: Unknown TMU state\n");
  53         }
  54 }
  55 #endif
  56
  57 struct local_info {
  58         struct cros_ec_dev *cros_ec_dev;        /* Pointer to cros_ec device */
  59         int cros_ec_err;                        /* Error for cros_ec, 0 if ok */
  60 };
  61
  62 static struct local_info local;
  63
  64 #ifdef CONFIG_USB_EHCI_EXYNOS
  65 int board_usb_vbus_init(void)
  66 {
  67         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  68                                                 samsung_get_base_gpio_part1();
  69
  70         /* Enable VBUS power switch */
  71         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  72
  73         /* VBUS turn ON time */
  74         mdelay(3);
  75
  76         return 0;
  77 }
  78 #endif
  79
  80 #ifdef CONFIG_SOUND_MAX98095
  81 static void  board_enable_audio_codec(void)
  82 {
  83         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  84                                                 samsung_get_base_gpio_part1();
  85
  86         /* Enable MAX98095 Codec */
  87         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  88         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  89 }
  90 #endif
  91
  92 struct cros_ec_dev *board_get_cros_ec_dev(void)
  93 {
  94         return local.cros_ec_dev;
  95 }
  96
  97 static int board_init_cros_ec_devices(const void *blob)
  98 {
  99         local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
 100         if (local.cros_ec_err)
 101                 return -1;  /* Will report in board_late_init() */
 102
 103         return 0;
 104 }
 105
 106 int board_init(void)
 107 {
 108         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 109
 110 #if defined CONFIG_EXYNOS_TMU
 111         if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
 112                 debug("%s: Failed to init TMU\n", __func__);
 113                 return -1;
 114         }
 115         boot_temp_check();
 116 #endif
 117
 118 #ifdef CONFIG_EXYNOS_SPI
 119         spi_init();
 120 #endif
 121
 122         if (board_init_cros_ec_devices(gd->fdt_blob))
 123                 return -1;
 124
 125 #ifdef CONFIG_USB_EHCI_EXYNOS
 126         board_usb_vbus_init();
 127 #endif
 128 #ifdef CONFIG_SOUND_MAX98095
 129         board_enable_audio_codec();
 130 #endif
 131         return 0;
 132 }
 133
 134 int dram_init(void)
 135 {
 136         int i;
 137         u32 addr;
 138
 139         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 140                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 141                 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 142         }
 143         return 0;
 144 }
 145
 146 #if defined(CONFIG_POWER)
 147 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
 148 {
 149         u32 val;
 150         int ret = 0;
 151
 152         ret = pmic_reg_read(p, reg, &val);
 153         if (ret) {
 154                 debug("%s: PMIC %d register read failed\n", __func__, reg);
 155                 return -1;
 156         }
 157         val |= regval;
 158         ret = pmic_reg_write(p, reg, val);
 159         if (ret) {
 160                 debug("%s: PMIC %d register write failed\n", __func__, reg);
 161                 return -1;
 162         }
 163         return 0;
 164 }
 165
 166 int power_init_board(void)
 167 {
 168         struct pmic *p;
 169
 170         set_ps_hold_ctrl();
 171
 172         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 173
 174         if (pmic_init(I2C_PMIC))
 175                 return -1;
 176
 177         p = pmic_get("MAX77686_PMIC");
 178         if (!p)
 179                 return -ENODEV;
 180
 181         if (pmic_probe(p))
 182                 return -1;
 183
 184         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 185                 return -1;
 186
 187         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 188                             MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 189                 return -1;
 190
 191         /* VDD_MIF */
 192         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 193                            MAX77686_BUCK1OUT_1V)) {
 194                 debug("%s: PMIC %d register write failed\n", __func__,
 195                       MAX77686_REG_PMIC_BUCK1OUT);
 196                 return -1;
 197         }
 198
 199         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 200                             MAX77686_BUCK1CTRL_EN))
 201                 return -1;
 202
 203         /* VDD_ARM */
 204         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 205                            MAX77686_BUCK2DVS1_1_3V)) {
 206                 debug("%s: PMIC %d register write failed\n", __func__,
 207                       MAX77686_REG_PMIC_BUCK2DVS1);
 208                 return -1;
 209         }
 210
 211         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 212                             MAX77686_BUCK2CTRL_ON))
 213                 return -1;
 214
 215         /* VDD_INT */
 216         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 217                            MAX77686_BUCK3DVS1_1_0125V)) {
 218                 debug("%s: PMIC %d register write failed\n", __func__,
 219                       MAX77686_REG_PMIC_BUCK3DVS1);
 220                 return -1;
 221         }
 222
 223         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 224                             MAX77686_BUCK3CTRL_ON))
 225                 return -1;
 226
 227         /* VDD_G3D */
 228         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 229                            MAX77686_BUCK4DVS1_1_2V)) {
 230                 debug("%s: PMIC %d register write failed\n", __func__,
 231                       MAX77686_REG_PMIC_BUCK4DVS1);
 232                 return -1;
 233         }
 234
 235         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 236                             MAX77686_BUCK3CTRL_ON))
 237                 return -1;
 238
 239         /* VDD_LDO2 */
 240         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 241                             MAX77686_LD02CTRL1_1_5V | EN_LDO))
 242                 return -1;
 243
 244         /* VDD_LDO3 */
 245         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 246                             MAX77686_LD03CTRL1_1_8V | EN_LDO))
 247                 return -1;
 248
 249         /* VDD_LDO5 */
 250         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 251                             MAX77686_LD05CTRL1_1_8V | EN_LDO))
 252                 return -1;
 253
 254         /* VDD_LDO10 */
 255         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 256                             MAX77686_LD10CTRL1_1_8V | EN_LDO))
 257                 return -1;
 258
 259         return 0;
 260 }
 261 #endif
 262
 263 void dram_init_banksize(void)
 264 {
 265         int i;
 266         u32 addr, size;
 267
 268         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 269                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 270                 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 271
 272                 gd->bd->bi_dram[i].start = addr;
 273                 gd->bd->bi_dram[i].size = size;
 274         }
 275 }
 276
 277 static int decode_sromc(const void *blob, struct fdt_sromc *config)
 278 {
 279         int err;
 280         int node;
 281
 282         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
 283         if (node < 0) {
 284                 debug("Could not find SROMC node\n");
 285                 return node;
 286         }
 287
 288         config->bank = fdtdec_get_int(blob, node, "bank", 0);
 289         config->width = fdtdec_get_int(blob, node, "width", 2);
 290
 291         err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
 292                         FDT_SROM_TIMING_COUNT);
 293         if (err < 0) {
 294                 debug("Could not decode SROMC configuration Error: %s\n",
 295                       fdt_strerror(err));
 296                 return -FDT_ERR_NOTFOUND;
 297         }
 298         return 0;
 299 }
 300
 301 int board_eth_init(bd_t *bis)
 302 {
 303 #ifdef CONFIG_SMC911X
 304         u32 smc_bw_conf, smc_bc_conf;
 305         struct fdt_sromc config;
 306         fdt_addr_t base_addr;
 307         int node;
 308
 309         node = decode_sromc(gd->fdt_blob, &config);
 310         if (node < 0) {
 311                 debug("%s: Could not find sromc configuration\n", __func__);
 312                 return 0;
 313         }
 314         node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
 315         if (node < 0) {
 316                 debug("%s: Could not find lan9215 configuration\n", __func__);
 317                 return 0;
 318         }
 319
 320         /* We now have a node, so any problems from now on are errors */
 321         base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
 322         if (base_addr == FDT_ADDR_T_NONE) {
 323                 debug("%s: Could not find lan9215 address\n", __func__);
 324                 return -1;
 325         }
 326
 327         /* Ethernet needs data bus width of 16 bits */
 328         if (config.width != 2) {
 329                 debug("%s: Unsupported bus width %d\n", __func__,
 330                       config.width);
 331                 return -1;
 332         }
 333         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 334                         | SROMC_BYTE_ENABLE(config.bank);
 335
 336         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
 337                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
 338                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
 339                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
 340                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
 341                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
 342                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 343
 344         /* Select and configure the SROMC bank */
 345         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 346         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 347         return smc911x_initialize(0, base_addr);
 348 #endif
 349         return 0;
 350 }
 351
 352 #ifdef CONFIG_DISPLAY_BOARDINFO
 353 int checkboard(void)
 354 {
 355         const char *board_name;
 356
 357         board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
 358         if (board_name == NULL)
 359                 printf("\nUnknown Board\n");
 360         else
 361                 printf("\nBoard: %s\n", board_name);
 362
 363         return 0;
 364 }
 365 #endif
 366
 367 #ifdef CONFIG_GENERIC_MMC
 368 int board_mmc_init(bd_t *bis)
 369 {
 370         int ret;
 371         /* dwmmc initializattion for available channels */
 372         ret = exynos_dwmmc_init(gd->fdt_blob);
 373         if (ret)
 374                 debug("dwmmc init failed\n");
 375
 376         return ret;
 377 }
 378 #endif
 379
 380 static int board_uart_init(void)
 381 {
 382         int err, uart_id, ret = 0;
 383
 384         for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
 385                 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
 386                 if (err) {
 387                         debug("UART%d not configured\n",
 388                               (uart_id - PERIPH_ID_UART0));
 389                         ret |= err;
 390                 }
 391         }
 392         return ret;
 393 }
 394
 395 #ifdef CONFIG_BOARD_EARLY_INIT_F
 396 int board_early_init_f(void)
 397 {
 398         int err;
 399         err = board_uart_init();
 400         if (err) {
 401                 debug("UART init failed\n");
 402                 return err;
 403         }
 404 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 405         board_i2c_init(gd->fdt_blob);
 406 #endif
 407         return err;
 408 }
 409 #endif
 410
 411 #ifdef CONFIG_LCD
 412 void exynos_cfg_lcd_gpio(void)
 413 {
 414         struct exynos5_gpio_part1 *gpio1 =
 415                 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
 416
 417         /* For Backlight */
 418         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 419         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 420
 421         /* LCD power on */
 422         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 423         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 424
 425         /* Set Hotplug detect for DP */
 426         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 427 }
 428
 429 void exynos_set_dp_phy(unsigned int onoff)
 430 {
 431         set_dp_phy_ctrl(onoff);
 432 }
 433 #endif
 434
 435 #ifdef CONFIG_BOARD_LATE_INIT
 436 int board_late_init(void)
 437 {
 438         stdio_print_current_devices();
 439
 440         if (local.cros_ec_err) {
 441                 /* Force console on */
 442                 gd->flags &= ~GD_FLG_SILENT;
 443
 444                 printf("cros-ec communications failure %d\n",
 445                        local.cros_ec_err);
 446                 puts("\nPlease reset with Power+Refresh\n\n");
 447                 panic("Cannot init cros-ec device");
 448                 return -1;
 449         }
 450         return 0;
 451 }
 452 #endif