2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/adc.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/mmc.h>
17 #include <asm/arch/pinmux.h>
18 #include <asm/arch/watchdog.h>
21 #include <power/pmic.h>
22 #include <usb/s3c_udc.h>
23 #include <asm/arch/cpu.h>
24 #include <power/max8998_pmic.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 struct exynos4_gpio_part1
*gpio1
;
29 struct exynos4_gpio_part2
*gpio2
;
30 unsigned int board_rev
;
32 u32
get_board_rev(void)
37 static int get_hwrev(void)
39 return board_rev
& 0xFF;
42 static void init_pmic_lcd(void);
44 int power_init_board(void)
49 * For PMIC the I2C bus is named as I2C5, but it is connected
50 * to logical I2C adapter 0
52 ret
= pmic_init(I2C_0
);
63 gd
->ram_size
= get_ram_size((long *)PHYS_SDRAM_1
, PHYS_SDRAM_1_SIZE
) +
64 get_ram_size((long *)PHYS_SDRAM_2
, PHYS_SDRAM_2_SIZE
);
69 void dram_init_banksize(void)
71 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
72 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
73 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
74 gd
->bd
->bi_dram
[1].size
= PHYS_SDRAM_2_SIZE
;
77 static unsigned short get_adc_value(int channel
)
79 struct s5p_adc
*adc
= (struct s5p_adc
*)samsung_get_base_adc();
80 unsigned short ret
= 0;
82 unsigned int loop
= 0;
84 writel(channel
& 0xF, &adc
->adcmux
);
85 writel((1 << 14) | (49 << 6), &adc
->adccon
);
86 writel(1000 & 0xffff, &adc
->adcdly
);
87 writel(readl(&adc
->adccon
) | (1 << 16), &adc
->adccon
); /* 12 bit */
89 writel(readl(&adc
->adccon
) | (1 << 0), &adc
->adccon
); /* Enable */
94 reg
= readl(&adc
->adccon
);
95 } while (!(reg
& (1 << 15)) && (loop
++ < 1000));
97 ret
= readl(&adc
->adcdat0
) & 0xFFF;
102 static int adc_power_control(int on
)
105 struct pmic
*p
= pmic_get("MAX8998_PMIC");
112 ret
= pmic_set_output(p
,
119 static unsigned int get_hw_revision(void)
121 int hwrev
, mode0
, mode1
;
123 adc_power_control(1);
125 mode0
= get_adc_value(1); /* HWREV_MODE0 */
126 mode1
= get_adc_value(2); /* HWREV_MODE1 */
129 * XXX Always set the default hwrev as the latest board
130 * ADC = (voltage) / 3.3 * 4096
134 #define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
135 if (IS_RANGE(mode0
, 80, 200) && IS_RANGE(mode1
, 80, 200))
136 hwrev
= 0x0; /* 0.01V 0.01V */
137 if (IS_RANGE(mode0
, 750, 1000) && IS_RANGE(mode1
, 80, 200))
138 hwrev
= 0x1; /* 610mV 0.01V */
139 if (IS_RANGE(mode0
, 1300, 1700) && IS_RANGE(mode1
, 80, 200))
140 hwrev
= 0x2; /* 1.16V 0.01V */
141 if (IS_RANGE(mode0
, 2000, 2400) && IS_RANGE(mode1
, 80, 200))
142 hwrev
= 0x3; /* 1.79V 0.01V */
145 debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0
, mode1
, hwrev
);
147 adc_power_control(0);
152 static void check_hw_revision(void)
156 hwrev
= get_hw_revision();
161 #ifdef CONFIG_DISPLAY_BOARDINFO
164 puts("Board:\tUniversal C210\n");
169 #ifdef CONFIG_GENERIC_MMC
170 int board_mmc_init(bd_t
*bis
)
174 switch (get_hwrev()) {
177 * Set the low to enable LDO_EN
178 * But when you use the test board for eMMC booting
179 * you should set it HIGH since it removes the inverter
181 /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
182 s5p_gpio_direction_output(&gpio1
->e3
, 6, 0);
186 * Default reset state is High and there's no inverter
187 * But set it as HIGH to ensure
189 /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
190 s5p_gpio_direction_output(&gpio1
->e1
, 3, 1);
196 * mmc0 : eMMC (8-bit buswidth)
197 * mmc2 : SD card (4-bit buswidth)
199 err
= exynos_pinmux_config(PERIPH_ID_SDMMC0
, PINMUX_FLAG_8BIT_MODE
);
201 debug("SDMMC0 not configured\n");
203 err
= s5p_mmc_init(0, 8);
206 s5p_gpio_cfg_pin(&gpio2
->x3
, 4, 0xf);
207 s5p_gpio_set_pull(&gpio2
->x3
, 4, GPIO_PULL_UP
);
210 * Check the T-flash detect pin
211 * GPX3[4] T-flash detect pin
213 if (!s5p_gpio_get_value(&gpio2
->x3
, 4)) {
214 err
= exynos_pinmux_config(PERIPH_ID_SDMMC2
, PINMUX_FLAG_NONE
);
216 debug("SDMMC2 not configured\n");
218 err
= s5p_mmc_init(2, 4);
226 #ifdef CONFIG_USB_GADGET
227 static int s5pc210_phy_control(int on
)
230 struct pmic
*p
= pmic_get("MAX8998_PMIC");
238 ret
|= pmic_set_output(p
,
239 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3
,
240 MAX8998_SAFEOUT1
, LDO_ON
);
241 ret
|= pmic_set_output(p
, MAX8998_REG_ONOFF1
,
242 MAX8998_LDO3
, LDO_ON
);
243 ret
|= pmic_set_output(p
, MAX8998_REG_ONOFF2
,
244 MAX8998_LDO8
, LDO_ON
);
247 ret
|= pmic_set_output(p
, MAX8998_REG_ONOFF2
,
248 MAX8998_LDO8
, LDO_OFF
);
249 ret
|= pmic_set_output(p
, MAX8998_REG_ONOFF1
,
250 MAX8998_LDO3
, LDO_OFF
);
251 ret
|= pmic_set_output(p
,
252 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3
,
253 MAX8998_SAFEOUT1
, LDO_OFF
);
257 puts("MAX8998 LDO setting error!\n");
264 struct s3c_plat_otg_data s5pc210_otg_data
= {
265 .phy_control
= s5pc210_phy_control
,
266 .regs_phy
= EXYNOS4_USBPHY_BASE
,
267 .regs_otg
= EXYNOS4_USBOTG_BASE
,
268 .usb_phy_ctrl
= EXYNOS4_USBPHY_CONTROL
,
269 .usb_flags
= PHY0_SLEEP
,
273 int board_early_init_f(void)
280 #ifdef CONFIG_SOFT_SPI
281 static void soft_spi_init(void)
283 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK
,
284 CONFIG_SOFT_SPI_MODE
& SPI_CPOL
);
285 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI
, 1);
286 gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO
);
287 gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS
,
288 !(CONFIG_SOFT_SPI_MODE
& SPI_CS_HIGH
));
291 void spi_cs_activate(struct spi_slave
*slave
)
293 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS
,
294 !(CONFIG_SOFT_SPI_MODE
& SPI_CS_HIGH
));
296 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS
,
297 CONFIG_SOFT_SPI_MODE
& SPI_CS_HIGH
);
300 void spi_cs_deactivate(struct spi_slave
*slave
)
302 gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS
,
303 !(CONFIG_SOFT_SPI_MODE
& SPI_CS_HIGH
));
306 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
308 return bus
== 0 && cs
== 0;
311 void universal_spi_scl(int bit
)
313 gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK
, bit
);
316 void universal_spi_sda(int bit
)
318 gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI
, bit
);
321 int universal_spi_read(void)
323 return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO
);
327 static void init_pmic_lcd(void)
332 struct pmic
*p
= pmic_get("MAX8998_PMIC");
341 val
= 0x02; /* (1800 - 1600) / 100; */
342 ret
|= pmic_reg_write(p
, MAX8998_REG_LDO7
, val
);
345 val
= 0xe; /* (3000 - 1600) / 100; */
346 ret
|= pmic_reg_write(p
, MAX8998_REG_LDO17
, val
);
348 /* Disable unneeded regulators */
351 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
352 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
355 ret
|= pmic_reg_write(p
, MAX8998_REG_ONOFF1
, val
);
358 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
359 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
362 ret
|= pmic_reg_write(p
, MAX8998_REG_ONOFF2
, val
);
365 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
366 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
369 ret
|= pmic_reg_write(p
, MAX8998_REG_ONOFF3
, val
);
372 puts("LCD pmic initialisation error!\n");
375 void exynos_cfg_lcd_gpio(void)
377 unsigned int i
, f3_end
= 4;
379 for (i
= 0; i
< 8; i
++) {
380 /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
381 s5p_gpio_cfg_pin(&gpio1
->f0
, i
, GPIO_FUNC(2));
382 s5p_gpio_cfg_pin(&gpio1
->f1
, i
, GPIO_FUNC(2));
383 s5p_gpio_cfg_pin(&gpio1
->f2
, i
, GPIO_FUNC(2));
384 /* pull-up/down disable */
385 s5p_gpio_set_pull(&gpio1
->f0
, i
, GPIO_PULL_NONE
);
386 s5p_gpio_set_pull(&gpio1
->f1
, i
, GPIO_PULL_NONE
);
387 s5p_gpio_set_pull(&gpio1
->f2
, i
, GPIO_PULL_NONE
);
389 /* drive strength to max (24bit) */
390 s5p_gpio_set_drv(&gpio1
->f0
, i
, GPIO_DRV_4X
);
391 s5p_gpio_set_rate(&gpio1
->f0
, i
, GPIO_DRV_SLOW
);
392 s5p_gpio_set_drv(&gpio1
->f1
, i
, GPIO_DRV_4X
);
393 s5p_gpio_set_rate(&gpio1
->f1
, i
, GPIO_DRV_SLOW
);
394 s5p_gpio_set_drv(&gpio1
->f2
, i
, GPIO_DRV_4X
);
395 s5p_gpio_set_rate(&gpio1
->f0
, i
, GPIO_DRV_SLOW
);
398 for (i
= 0; i
< f3_end
; i
++) {
399 /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
400 s5p_gpio_cfg_pin(&gpio1
->f3
, i
, GPIO_FUNC(2));
401 /* pull-up/down disable */
402 s5p_gpio_set_pull(&gpio1
->f3
, i
, GPIO_PULL_NONE
);
403 /* drive strength to max (24bit) */
404 s5p_gpio_set_drv(&gpio1
->f3
, i
, GPIO_DRV_4X
);
405 s5p_gpio_set_rate(&gpio1
->f3
, i
, GPIO_DRV_SLOW
);
408 /* gpio pad configuration for LCD reset. */
409 s5p_gpio_cfg_pin(&gpio2
->y4
, 5, GPIO_OUTPUT
);
414 void exynos_reset_lcd(void)
416 s5p_gpio_set_value(&gpio2
->y4
, 5, 1);
418 s5p_gpio_set_value(&gpio2
->y4
, 5, 0);
420 s5p_gpio_set_value(&gpio2
->y4
, 5, 1);
424 void exynos_lcd_power_on(void)
426 struct pmic
*p
= pmic_get("MAX8998_PMIC");
434 pmic_set_output(p
, MAX8998_REG_ONOFF3
, MAX8998_LDO17
, LDO_ON
);
435 pmic_set_output(p
, MAX8998_REG_ONOFF2
, MAX8998_LDO7
, LDO_ON
);
438 vidinfo_t panel_info
= {
444 .vl_clkp
= CONFIG_SYS_HIGH
,
445 .vl_hsp
= CONFIG_SYS_HIGH
,
446 .vl_vsp
= CONFIG_SYS_HIGH
,
447 .vl_dp
= CONFIG_SYS_HIGH
,
449 .vl_bpix
= 5, /* Bits per pixel */
451 /* LD9040 LCD Panel */
459 .vl_cmd_allow_len
= 0xf,
462 .dual_lcd_enabled
= 0,
465 .power_on_delay
= 10000,
466 .reset_delay
= 10000,
467 .interface_mode
= FIMD_RGB_INTERFACE
,
471 void exynos_cfg_ldo(void)
476 void exynos_enable_ldo(unsigned int onoff
)
478 ld9040_enable_ldo(onoff
);
481 void init_panel_info(vidinfo_t
*vid
)
484 vid
->resolution
= HD_RESOLUTION
;
485 vid
->rgb_mode
= MODE_RGB_P
;
488 get_tizen_logo_info(vid
);
492 vid
->pclk_name
= 1; /* MPLL */
495 setenv("lcdinfo", "lcd=ld9040");
500 gpio1
= (struct exynos4_gpio_part1
*) EXYNOS4_GPIO_PART1_BASE
;
501 gpio2
= (struct exynos4_gpio_part2
*) EXYNOS4_GPIO_PART2_BASE
;
503 gd
->bd
->bi_arch_number
= MACH_TYPE_UNIVERSAL_C210
;
504 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
506 #ifdef CONFIG_SOFT_SPI
510 printf("HW Revision:\t0x%x\n", board_rev
);
515 #ifdef CONFIG_MISC_INIT_R
516 int misc_init_r(void)
518 #ifdef CONFIG_CMD_BMP
519 if (panel_info
.logo_on
)