board/sandburst/common/ppc440gx_i2c.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
   9  * Travis B. Sawyer
  10  * Sandburst Corporation.
  11  */
  12 #include <common.h>
  13 #include <asm/ppc4xx.h>
  14 #include <asm/ppc4xx-i2c.h>
  15 #include <i2c.h>
  16 #include <command.h>
  17 #include "ppc440gx_i2c.h"
  18 #include <asm/io.h>
  19
  20 #ifdef CONFIG_I2C_BUS1
  21
  22 #define IIC_OK          0
  23 #define IIC_NOK         1
  24 #define IIC_NOK_LA      2               /* Lost arbitration */
  25 #define IIC_NOK_ICT     3               /* Incomplete transfer */
  26 #define IIC_NOK_XFRA    4               /* Transfer aborted */
  27 #define IIC_NOK_DATA    5               /* No data in buffer */
  28 #define IIC_NOK_TOUT    6               /* Transfer timeout */
  29
  30 #define IIC_TIMEOUT 1                   /* 1 second */
  31 #if defined(CONFIG_SYS_I2C_NOPROBES)
  32 static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
  33 #endif
  34
  35 static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
  36
  37 static void _i2c_bus1_reset (void)
  38 {
  39         int i, status;
  40
  41         /* Reset status register */
  42         /* write 1 in SCMP and IRQA to clear these fields */
  43         out_8 (IIC_STS1, 0x0A);
  44
  45         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  46         out_8 (IIC_EXTSTS1, 0x8F);
  47         __asm__ volatile ("eieio");
  48
  49         /*
  50          * Get current state, reset bus
  51          * only if no transfers are pending.
  52          */
  53         i = 10;
  54         do {
  55                 /* Get status */
  56                 status = in_8 (IIC_STS1);
  57                 udelay (500);                   /* 500us */
  58                 i--;
  59         } while ((status & IIC_STS_PT) && (i > 0));
  60         /* Soft reset controller */
  61         status = in_8 (IIC_XTCNTLSS1);
  62         out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
  63         __asm__ volatile ("eieio");
  64
  65         /* make sure where in initial state, data hi, clock hi */
  66         out_8 (IIC_DIRECTCNTL1, 0xC);
  67         for (i = 0; i < 10; i++) {
  68                 if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
  69                         /* clock until we get to known state */
  70                         out_8 (IIC_DIRECTCNTL1, 0x8);   /* clock lo */
  71                         udelay (100);           /* 100us */
  72                         out_8 (IIC_DIRECTCNTL1, 0xC);   /* clock hi */
  73                         udelay (100);           /* 100us */
  74                 } else {
  75                         break;
  76                 }
  77         }
  78         /* send start condition */
  79         out_8 (IIC_DIRECTCNTL1, 0x4);
  80         udelay (1000);                          /* 1ms */
  81         /* send stop condition */
  82         out_8 (IIC_DIRECTCNTL1, 0xC);
  83         udelay (1000);                          /* 1ms */
  84         /* Unreset controller */
  85         out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
  86         udelay (1000);                          /* 1ms */
  87 }
  88
  89 void i2c1_init (int speed, int slaveadd)
  90 {
  91         sys_info_t sysInfo;
  92         unsigned long freqOPB;
  93         int val, divisor;
  94
  95 #ifdef CONFIG_SYS_I2C_INIT_BOARD
  96         /* call board specific i2c bus reset routine before accessing the   */
  97         /* environment, which might be in a chip on that bus. For details   */
  98         /* about this problem see doc/I2C_Edge_Conditions.                  */
  99         i2c_init_board();
 100 #endif
 101
 102         /* Handle possible failed I2C state */
 103         /* FIXME: put this into i2c_init_board()? */
 104         _i2c_bus1_reset ();
 105
 106         /* clear lo master address */
 107         out_8 (IIC_LMADR1, 0);
 108
 109         /* clear hi master address */
 110         out_8 (IIC_HMADR1, 0);
 111
 112         /* clear lo slave address */
 113         out_8 (IIC_LSADR1, 0);
 114
 115         /* clear hi slave address */
 116         out_8 (IIC_HSADR1, 0);
 117
 118         /* Clock divide Register */
 119         /* get OPB frequency */
 120         get_sys_info (&sysInfo);
 121         freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
 122         /* set divisor according to freqOPB */
 123         divisor = (freqOPB - 1) / 10000000;
 124         if (divisor == 0)
 125                 divisor = 1;
 126         out_8 (IIC_CLKDIV1, divisor);
 127
 128         /* no interrupts */
 129         out_8 (IIC_INTRMSK1, 0);
 130
 131         /* clear transfer count */
 132         out_8 (IIC_XFRCNT1, 0);
 133
 134         /* clear extended control & stat */
 135         /* write 1 in SRC SRS SWC SWS to clear these fields */
 136         out_8 (IIC_XTCNTLSS1, 0xF0);
 137
 138         /* Mode Control Register
 139            Flush Slave/Master data buffer */
 140         out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 141         __asm__ volatile ("eieio");
 142
 143
 144         val = in_8(IIC_MDCNTL1);
 145         __asm__ volatile ("eieio");
 146
 147         /* Ignore General Call, slave transfers are ignored,
 148            disable interrupts, exit unknown bus state, enable hold
 149            SCL
 150            100kHz normaly or FastMode for 400kHz and above
 151         */
 152
 153         val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
 154         if( speed >= 400000 ){
 155                 val |= IIC_MDCNTL_FSM;
 156         }
 157         out_8 (IIC_MDCNTL1, val);
 158
 159         /* clear control reg */
 160         out_8 (IIC_CNTL1, 0x00);
 161         __asm__ volatile ("eieio");
 162
 163 }
 164
 165 /*
 166   This code tries to use the features of the 405GP i2c
 167   controller. It will transfer up to 4 bytes in one pass
 168   on the loop. It only does out_8(lbz) to the buffer when it
 169   is possible to do out16(lhz) transfers.
 170
 171   cmd_type is 0 for write 1 for read.
 172
 173   addr_len can take any value from 0-255, it is only limited
 174   by the char, we could make it larger if needed. If it is
 175   0 we skip the address write cycle.
 176
 177   Typical case is a Write of an addr followd by a Read. The
 178   IBM FAQ does not cover this. On the last byte of the write
 179   we don't set the creg CHT bit, and on the first bytes of the
 180   read we set the RPST bit.
 181
 182   It does not support address only transfers, there must be
 183   a data part. If you want to write the address yourself, put
 184   it in the data pointer.
 185
 186   It does not support transfer to/from address 0.
 187
 188   It does not check XFRCNT.
 189 */
 190 static
 191 int i2c_transfer1(unsigned char cmd_type,
 192                   unsigned char chip,
 193                   unsigned char addr[],
 194                   unsigned char addr_len,
 195                   unsigned char data[],
 196                   unsigned short data_len )
 197 {
 198         unsigned char* ptr;
 199         int reading;
 200         int tran,cnt;
 201         int result;
 202         int status;
 203         int i;
 204         uchar creg;
 205
 206         if( data == 0 || data_len == 0 ){
 207                 /*Don't support data transfer of no length or to address 0*/
 208                 printf( "i2c_transfer: bad call\n" );
 209                 return IIC_NOK;
 210         }
 211         if( addr && addr_len ){
 212                 ptr = addr;
 213                 cnt = addr_len;
 214                 reading = 0;
 215         }else{
 216                 ptr = data;
 217                 cnt = data_len;
 218                 reading = cmd_type;
 219         }
 220
 221         /*Clear Stop Complete Bit*/
 222         out_8(IIC_STS1,IIC_STS_SCMP);
 223         /* Check init */
 224         i=10;
 225         do {
 226                 /* Get status */
 227                 status = in_8(IIC_STS1);
 228                 __asm__ volatile("eieio");
 229                 i--;
 230         } while ((status & IIC_STS_PT) && (i>0));
 231
 232         if (status & IIC_STS_PT) {
 233                 result = IIC_NOK_TOUT;
 234                 return(result);
 235         }
 236         /*flush the Master/Slave Databuffers*/
 237         out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
 238         /*need to wait 4 OPB clocks? code below should take that long*/
 239
 240         /* 7-bit adressing */
 241         out_8(IIC_HMADR1,0);
 242         out_8(IIC_LMADR1, chip);
 243         __asm__ volatile("eieio");
 244
 245         tran = 0;
 246         result = IIC_OK;
 247         creg = 0;
 248
 249         while ( tran != cnt && (result == IIC_OK)) {
 250                 int  bc,j;
 251
 252                 /* Control register =
 253                    Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
 254                    Transfer is a sequence of transfers
 255                 */
 256                 creg |= IIC_CNTL_PT;
 257
 258                 bc = (cnt - tran) > 4 ? 4 :
 259                         cnt - tran;
 260                 creg |= (bc-1)<<4;
 261                 /* if the real cmd type is write continue trans*/
 262                 if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
 263                         creg |= IIC_CNTL_CHT;
 264
 265                 if (reading)
 266                         creg |= IIC_CNTL_READ;
 267                 else {
 268                         for(j=0; j<bc; j++) {
 269                                 /* Set buffer */
 270                                 out_8(IIC_MDBUF1,ptr[tran+j]);
 271                                 __asm__ volatile("eieio");
 272                         }
 273                 }
 274                 out_8(IIC_CNTL1, creg );
 275                 __asm__ volatile("eieio");
 276
 277                 /* Transfer is in progress
 278                    we have to wait for upto 5 bytes of data
 279                    1 byte chip address+r/w bit then bc bytes
 280                    of data.
 281                    udelay(10) is 1 bit time at 100khz
 282                    Doubled for slop. 20 is too small.
 283                 */
 284                 i=2*5*8;
 285                 do {
 286                         /* Get status */
 287                         status = in_8(IIC_STS1);
 288                         __asm__ volatile("eieio");
 289                         udelay (10);
 290                         i--;
 291                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
 292                          && (i>0));
 293
 294                 if (status & IIC_STS_ERR) {
 295                         result = IIC_NOK;
 296                         status = in_8 (IIC_EXTSTS1);
 297                         /* Lost arbitration? */
 298                         if (status & IIC_EXTSTS_LA)
 299                                 result = IIC_NOK_LA;
 300                         /* Incomplete transfer? */
 301                         if (status & IIC_EXTSTS_ICT)
 302                                 result = IIC_NOK_ICT;
 303                         /* Transfer aborted? */
 304                         if (status & IIC_EXTSTS_XFRA)
 305                                 result = IIC_NOK_XFRA;
 306                 } else if ( status & IIC_STS_PT) {
 307                         result = IIC_NOK_TOUT;
 308                 }
 309                 /* Command is reading => get buffer */
 310                 if ((reading) && (result == IIC_OK)) {
 311                         /* Are there data in buffer */
 312                         if (status & IIC_STS_MDBS) {
 313                                 /*
 314                                   even if we have data we have to wait 4OPB clocks
 315                                   for it to hit the front of the FIFO, after that
 316                                   we can just read. We should check XFCNT here and
 317                                   if the FIFO is full there is no need to wait.
 318                                 */
 319                                 udelay (1);
 320                                 for(j=0;j<bc;j++) {
 321                                         ptr[tran+j] = in_8(IIC_MDBUF1);
 322                                         __asm__ volatile("eieio");
 323                                 }
 324                         } else
 325                                 result = IIC_NOK_DATA;
 326                 }
 327                 creg = 0;
 328                 tran+=bc;
 329                 if( ptr == addr && tran == cnt ) {
 330                         ptr = data;
 331                         cnt = data_len;
 332                         tran = 0;
 333                         reading = cmd_type;
 334                         if( reading )
 335                                 creg = IIC_CNTL_RPST;
 336                 }
 337         }
 338         return (result);
 339 }
 340
 341 int i2c_probe1 (uchar chip)
 342 {
 343         uchar buf[1];
 344
 345         buf[0] = 0;
 346
 347         /*
 348          * What is needed is to send the chip address and verify that the
 349          * address was <ACK>ed (i.e. there was a chip at that address which
 350          * drove the data line low).
 351          */
 352         return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
 353 }
 354
 355
 356 int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
 357 {
 358         uchar xaddr[4];
 359         int ret;
 360
 361         if ( alen > 4 ) {
 362                 printf ("I2C read: addr len %d not supported\n", alen);
 363                 return 1;
 364         }
 365
 366         if ( alen > 0 ) {
 367                 xaddr[0] = (addr >> 24) & 0xFF;
 368                 xaddr[1] = (addr >> 16) & 0xFF;
 369                 xaddr[2] = (addr >> 8) & 0xFF;
 370                 xaddr[3] = addr & 0xFF;
 371         }
 372
 373
 374 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 375         /*
 376          * EEPROM chips that implement "address overflow" are ones
 377          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 378          * address and the extra bits end up in the "chip address"
 379          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 380          * four 256 byte chips.
 381          *
 382          * Note that we consider the length of the address field to
 383          * still be one byte because the extra address bits are
 384          * hidden in the chip address.
 385          */
 386         if( alen > 0 )
 387                 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 388 #endif
 389         if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
 390                 printf( "I2c read: failed %d\n", ret);
 391                 return 1;
 392         }
 393         return 0;
 394 }
 395
 396 int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
 397 {
 398         uchar xaddr[4];
 399
 400         if ( alen > 4 ) {
 401                 printf ("I2C write: addr len %d not supported\n", alen);
 402                 return 1;
 403
 404         }
 405         if ( alen > 0 ) {
 406                 xaddr[0] = (addr >> 24) & 0xFF;
 407                 xaddr[1] = (addr >> 16) & 0xFF;
 408                 xaddr[2] = (addr >> 8) & 0xFF;
 409                 xaddr[3] = addr & 0xFF;
 410         }
 411
 412 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 413         /*
 414          * EEPROM chips that implement "address overflow" are ones
 415          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 416          * address and the extra bits end up in the "chip address"
 417          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 418          * four 256 byte chips.
 419          *
 420          * Note that we consider the length of the address field to
 421          * still be one byte because the extra address bits are
 422          * hidden in the chip address.
 423          */
 424         if( alen > 0 )
 425                 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 426 #endif
 427
 428         return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 429 }
 430
 431 /*-----------------------------------------------------------------------
 432  * Read a register
 433  */
 434 uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
 435 {
 436         uchar buf;
 437
 438         i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
 439
 440         return(buf);
 441 }
 442
 443 /*-----------------------------------------------------------------------
 444  * Write a register
 445  */
 446 void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
 447 {
 448         i2c_write1(i2c_addr, reg, 1, &val, 1);
 449 }
 450
 451
 452 int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 453 {
 454         int j;
 455 #if defined(CONFIG_SYS_I2C_NOPROBES)
 456         int k, skip;
 457 #endif
 458
 459         puts ("Valid chip addresses:");
 460         for(j = 0; j < 128; j++) {
 461 #if defined(CONFIG_SYS_I2C_NOPROBES)
 462                 skip = 0;
 463                 for (k = 0; k < sizeof(i2c_no_probes); k++){
 464                         if (j == i2c_no_probes[k]){
 465                                 skip = 1;
 466                                 break;
 467                         }
 468                 }
 469                 if (skip)
 470                         continue;
 471 #endif
 472                 if(i2c_probe1(j) == 0) {
 473                         printf(" %02X", j);
 474                 }
 475         }
 476         putc ('\n');
 477
 478 #if defined(CONFIG_SYS_I2C_NOPROBES)
 479         puts ("Excluded chip addresses:");
 480         for( k = 0; k < sizeof(i2c_no_probes); k++ )
 481                 printf(" %02X", i2c_no_probes[k] );
 482         putc ('\n');
 483 #endif
 484
 485         return 0;
 486 }
 487
 488 U_BOOT_CMD(
 489         iprobe1,        1,      1,      do_i2c1_probe,
 490         "probe to discover valid I2C chip addresses",
 491         ""
 492 );
 493
 494 #endif  /* CONFIG_I2C_BUS1 */