board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <asm/processor.h>
  30 #include <asm/io.h>
  31 #include <spd_sdram.h>
  32 #include <i2c.h>
  33 #include "../common/sb_common.h"
  34 #include "../common/ppc440gx_i2c.h"
  35
  36 void fpga_init (void);
  37
  38 KAREF_BOARD_ID_ST board_id_as[] =
  39 {
  40         {"Undefined"},                       /* Not specified */
  41         {"Kamino Reference Design"},
  42         {"Reserved"},                        /* Reserved for future use */
  43         {"Reserved"},                        /* Reserved for future use */
  44 };
  45
  46 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  47 {
  48         {"Undefined"},
  49         {"1x10 + 10x2"},
  50         {"Reserved"},
  51         {"Reserved"},
  52 };
  53
  54 /*************************************************************************
  55  *  board_early_init_f
  56  *
  57  *  Setup chip selects, initialize the Opto-FPGA, initialize
  58  *  interrupt polarity and triggers.
  59  ************************************************************************/
  60 int board_early_init_f (void)
  61 {
  62         ppc440_gpio_regs_t *gpio_regs;
  63
  64         /* Enable GPIO interrupts */
  65         mtsdr(sdr_pfc0, 0x00103E00);
  66
  67         /* Setup access for LEDs, and system topology info */
  68         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  69         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  70         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  71
  72         /* Turn on all the leds for now */
  73         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  74
  75         /*--------------------------------------------------------------------+
  76           | Initialize EBC CONFIG
  77           +-------------------------------------------------------------------*/
  78         mtebc(xbcfg,
  79               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  80               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  81               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  82               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  83               EBC_CFG_PR_32);
  84
  85         /*--------------------------------------------------------------------+
  86           | 1/2 MB FLASH. Initialize bank 0 with default values.
  87           +-------------------------------------------------------------------*/
  88         mtebc(pb0ap,
  89               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  90               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  91               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  92               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  93               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  94               EBC_BXAP_PEN_DISABLED);
  95
  96         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  97               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  98         /*--------------------------------------------------------------------+
  99           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 100           +-------------------------------------------------------------------*/
 101         mtebc(pb1ap,
 102               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 103               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 104               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 105               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 106               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 107               EBC_BXAP_PEN_DISABLED);
 108
 109         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 110               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 111
 112         /*--------------------------------------------------------------------+
 113           | Compact Flash, uses 2 Chip Selects (2 & 6)
 114           +-------------------------------------------------------------------*/
 115         mtebc(pb2ap,
 116               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 117               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 118               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 119               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 120               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 121               EBC_BXAP_PEN_DISABLED);
 122
 123         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 124               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 125
 126         /*--------------------------------------------------------------------+
 127           | KaRef Scan FPGA. Initialize bank 3 with default values.
 128           +-------------------------------------------------------------------*/
 129         mtebc(pb5ap,
 130               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 131               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 132               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 133               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 134               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 135
 136         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 137               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 138
 139         /*--------------------------------------------------------------------+
 140           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 141           | Initialize bank 4 with default values.
 142           +-------------------------------------------------------------------*/
 143         mtebc(pb4ap,
 144               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 145               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 146               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 147               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 148               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 149
 150         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 151               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 152
 153         /*--------------------------------------------------------------------+
 154           | OFEM FPGA  Initialize bank 5 with default values.
 155           +-------------------------------------------------------------------*/
 156         mtebc(pb3ap,
 157               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 158               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 159               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 160               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 161               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 162
 163
 164         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
 165               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 166
 167
 168         /*--------------------------------------------------------------------+
 169           | Compact Flash, uses 2 Chip Selects (2 & 6)
 170           +-------------------------------------------------------------------*/
 171         mtebc(pb6ap,
 172               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 173               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 174               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 175               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 176               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 177               EBC_BXAP_PEN_DISABLED);
 178
 179         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 180               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 181
 182         /*--------------------------------------------------------------------+
 183           | BME-32. Initialize bank 7 with default values.
 184           +-------------------------------------------------------------------*/
 185         mtebc(pb7ap,
 186               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 187               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 188               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 189               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 190               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 191
 192         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 193               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 194
 195         /*--------------------------------------------------------------------+
 196          * Setup the interrupt controller polarities, triggers, etc.
 197          +-------------------------------------------------------------------*/
 198         /*
 199          * Because of the interrupt handling rework to handle 440GX interrupts
 200          * with the common code, we needed to change names of the UIC registers.
 201          * Here the new relationship:
 202          *
 203          * U-Boot name  440GX name
 204          * -----------------------
 205          * UIC0         UICB0
 206          * UIC1         UIC0
 207          * UIC2         UIC1
 208          * UIC3         UIC2
 209          */
 210         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 211         mtdcr (uic1er, 0x00000000);     /* disable all */
 212         mtdcr (uic1cr, 0x00000000);     /* all non- critical */
 213         mtdcr (uic1pr, 0xfffffe03);     /* polarity */
 214         mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
 215         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 216         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 217
 218         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 219         mtdcr (uic2er, 0x00000000);     /* disable all */
 220         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 221         mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
 222         mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
 223         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 224         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 225
 226         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 227         mtdcr (uic3er, 0x00000000);     /* disable all */
 228         mtdcr (uic3cr, 0x00000000);     /* all non-critical */
 229         mtdcr (uic3pr, 0xffff83ff);     /* polarity */
 230         mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
 231         mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
 232         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 233
 234         mtdcr (uic0sr, 0xfc000000);     /* clear all */
 235         mtdcr (uic0er, 0x00000000);     /* disable all */
 236         mtdcr (uic0cr, 0x00000000);     /* all non-critical */
 237         mtdcr (uic0pr, 0xfc000000);
 238         mtdcr (uic0tr, 0x00000000);
 239         mtdcr (uic0vr, 0x00000001);
 240
 241         fpga_init();
 242
 243         return 0;
 244 }
 245
 246
 247 /*************************************************************************
 248  *  checkboard
 249  *
 250  *  Dump pertinent info to the console
 251  ************************************************************************/
 252 int checkboard (void)
 253 {
 254         sys_info_t sysinfo;
 255         unsigned char brd_rev, brd_id;
 256         unsigned short sernum;
 257         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 258         unsigned char ofem_brd_rev, ofem_brd_id;
 259         KAREF_FPGA_REGS_ST *karef_ps;
 260         OFEM_FPGA_REGS_ST *ofem_ps;
 261
 262         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 263         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 264
 265         scan_id = (unsigned char)((karef_ps->revision_ul &
 266                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 267                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 268
 269         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 270                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 271
 272         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 273                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 274
 275         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 276                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 277
 278         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 279                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 280
 281         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 282                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 283
 284         if (0xF != ofem_brd_id) {
 285                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 286                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 287                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 288
 289                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 290                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 291                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 292         }
 293
 294         get_sys_info (&sysinfo);
 295
 296         sernum = sbcommon_get_serial_number();
 297
 298         printf ("Board: Sandburst Corporation Kamino Reference Design "
 299                 "Serial Number: %d\n", sernum);
 300         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 301
 302         printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
 303         if (sbcommon_get_master()) {
 304                 printf("Slot 0 - Master\nSlave board");
 305                 if (sbcommon_secondary_present())
 306                         printf(" present\n");
 307                 else
 308                         printf(" not detected\n");
 309         } else {
 310                 printf("Slot 1 - Slave\n\n");
 311         }
 312
 313         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 314         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 315         if(0xF != ofem_brd_id) {
 316                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 317                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 318         }
 319
 320         /* Fix the ack in the bme 32 */
 321         udelay(5000);
 322         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 323         asm("eieio");
 324
 325
 326         return (0);
 327 }
 328
 329 /*************************************************************************
 330  *  misc_init_f
 331  *
 332  *  Initialize I2C bus one to gain access to the fans
 333  ************************************************************************/
 334 int misc_init_f (void)
 335 {
 336         /* Turn on i2c bus 1 */
 337         puts ("I2C1:  ");
 338         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 339         puts ("ready\n");
 340
 341         /* Turn on fans 3 & 4 */
 342         sbcommon_fans();
 343
 344         return (0);
 345 }
 346
 347 /*************************************************************************
 348  *  misc_init_r
 349  *
 350  *  Do nothing.
 351  ************************************************************************/
 352 int misc_init_r (void)
 353 {
 354         unsigned short sernum;
 355         char envstr[255];
 356         KAREF_FPGA_REGS_ST *karef_ps;
 357         OFEM_FPGA_REGS_ST *ofem_ps;
 358
 359         if(NULL != getenv("secondserial")) {
 360                 puts("secondserial is set, switching to second serial port\n");
 361                 setenv("stderr", "serial1");
 362                 setenv("stdout", "serial1");
 363                 setenv("stdin", "serial1");
 364         }
 365
 366         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 367
 368         memset(envstr, 0, 255);
 369         sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
 370         setenv("bldstr", envstr);
 371         saveenv();
 372
 373         if( getenv("autorecover")) {
 374                 setenv("autorecover", NULL);
 375                 saveenv();
 376                 sernum = sbcommon_get_serial_number();
 377
 378                 printf("\nSetting up environment for automatic filesystem recovery\n");
 379                 /*
 380                  * Setup default bootargs
 381                  */
 382                 memset(envstr, 0, 255);
 383
 384                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 385                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 386                         sernum, sernum);
 387                 setenv("bootargs", envstr);
 388
 389                 /*
 390                  * Setup Default boot command
 391                  */
 392                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 393                        "fatload ide 0 8100000 pramdisk;"
 394                        "bootm 8000000 8100000");
 395
 396                 printf("Done.  Please type allow the system to continue to boot\n");
 397         }
 398
 399         if( getenv("fakeled")) {
 400                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 401                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 402                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 403                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 404                 setenv("bootdelay", "-1");
 405                 saveenv();
 406                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 407         }
 408
 409         return (0);
 410 }
 411
 412 /*************************************************************************
 413  *  ide_set_reset
 414  ************************************************************************/
 415 #ifdef CONFIG_IDE_RESET
 416 void ide_set_reset(int on)
 417 {
 418         KAREF_FPGA_REGS_ST *karef_ps;
 419         /* TODO: ide reset */
 420         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 421
 422         if (on) {
 423                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 424         } else {
 425                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 426         }
 427 }
 428 #endif /* CONFIG_IDE_RESET */
 429
 430 /*************************************************************************
 431  *  fpga_init
 432  ************************************************************************/
 433 void fpga_init(void)
 434 {
 435         KAREF_FPGA_REGS_ST *karef_ps;
 436         OFEM_FPGA_REGS_ST *ofem_ps;
 437         unsigned char ofem_id;
 438         unsigned long tmp;
 439
 440         /* Ensure we have power all around */
 441         udelay(500);
 442
 443         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 444         tmp =
 445                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 446                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 447                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 448                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 449                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 450                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 451                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 452                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 453                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 454
 455         karef_ps->reset_ul = tmp;
 456
 457         /*
 458          * Wait a bit to allow the ofem fpga to get its brains
 459          */
 460         udelay(5000);
 461
 462         /*
 463          * Check to see if the ofem is there
 464          */
 465         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 466                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 467         if(0xF != ofem_id) {
 468                 tmp =
 469                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 470                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 471                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 472
 473                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 474                 ofem_ps->reset_ul = tmp;
 475
 476                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 477         }
 478
 479         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 480
 481         asm("eieio");
 482
 483         return;
 484 }
 485
 486 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 487 {
 488         unsigned short sernum;
 489         char envstr[255];
 490
 491         sernum = sbcommon_get_serial_number();
 492
 493         memset(envstr, 0, 255);
 494         /*
 495          * Setup our ip address
 496          */
 497         sprintf(envstr, "10.100.70.%d", sernum);
 498
 499         setenv("ipaddr", envstr);
 500         /*
 501          * Setup the host ip address
 502          */
 503         setenv("serverip", "10.100.17.10");
 504
 505         /*
 506          * Setup default bootargs
 507          */
 508         memset(envstr, 0, 255);
 509
 510         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 511                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 512                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 513                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 514                 sernum, sernum, sernum);
 515
 516         setenv("bootargs_nfs", envstr);
 517         setenv("bootargs", envstr);
 518
 519         /*
 520          * Setup CF bootargs
 521          */
 522         memset(envstr, 0, 255);
 523
 524         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 525                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 526                 sernum, sernum);
 527
 528         setenv("bootargs_cf", envstr);
 529
 530         /*
 531          * Setup Default boot command
 532          */
 533         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 534         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 535
 536         /*
 537          * Setup compact flash boot command
 538          */
 539         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 540
 541         saveenv();
 542
 543         return(1);
 544 }
 545
 546 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 547 {
 548         unsigned short sernum;
 549         char envstr[255];
 550
 551         sernum = sbcommon_get_serial_number();
 552
 553         printf("\nSetting up environment for filesystem recovery\n");
 554         /*
 555          * Setup default bootargs
 556          */
 557         memset(envstr, 0, 255);
 558
 559         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 560                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 561                 sernum, sernum);
 562         setenv("bootargs", envstr);
 563
 564         /*
 565          * Setup Default boot command
 566          */
 567
 568         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 569                "fatload ide 0 8100000 pramdisk;"
 570                "bootm 8000000 8100000");
 571
 572         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 573                " please type fsrecover.sh<cr>\n");
 574
 575         return(1);
 576 }
 577
 578 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 579            "kasetup - Set environment to factory defaults\n", NULL);
 580
 581 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 582            "karecover - Set environment to allow for fs recovery\n", NULL);